Delta39K™ ISR™
CPLD Family
PRELIMINARY
REVISIONS MADE TO THE DATA SHEET
Change
#
Revision
Date
Revision Description
on the first page the no fanout or expander delays has been removed.
Multiple I/O standards supported
Simple Timing Model
1)
2)
Under
12/7/1999
12/7
Under the bullet
been listed
section on the first page the I/o standards have
High Performance CPLDs
On the first page, in the top right corner “
at FPGA densities”
CPLDs
” has been changed to “
3)
12/7
Development Software
4)
5)
On the front page all software bullets have been put under the heading
Warp 3
12/7
12/7
Hierarchy Navi-
On the front page under the bullet the following items have been deleted:
gator, Warp Galaxy GUI for Input, Mixed-mode Design Entry for VHDL and Schematics, Avail-
able for PC, Sun, and HP platforms for $4995,
ucts
Supports all Cypress Programmable Prod-
and
Delta39K Speed Bins
the 15, 30, 50, and 100 macrocell devices.
6)
7)
In the
table the 154 MHz speed bins have been removed from all devices in
12/7
12/7
Delta39K Speed Bins
In the
table the 125 MHz speed bins have been added to all devices in the
15, 30, 50, and 100 macrocell devices.
Delta39K Speed Bins
8)
In the
In the
In the
table a 250 MHz speed bin column has been added.
12/7
12/7
12/7
Device Package Offerings
9)
table the 352-FBGA heading has been changed to 352-BGA
General Description
10)
section the sentence “With devices ranging from 50,000 to 350,000
usable gates....” has been changed to “...”.....15,000 to 350,000 usable gates.”
General Description
11)
12)
In the
disabled” has been removed
section the sentence “On device power up, the bus hold feature is
12/7
12/7
Global Routing Description
In the
section the sentence “Figure 2 is a block diagram of the routing
channels and all of the LBC PIM interfaces required in the Delta39K architecture” has been changed
to “Figure 2 is a block diagram of the routing channels that interfaces with the Delta39K architecture.”
Global Routing Description
The last sentence of
LBC.” has been removed.
13)
“Figure 3 shows a block diagram of the Delta39K
12/7
14)
15)
16)
In Figure 3 the numbering of the Logic Blocks and Cluster memories in the diagram were changed.
Macrocell
12/7
12/7
12/7
Carry Chain Logic section under the
description
In the FIFO Configuration section the sentence “These clocks may be tied together for a single
operation or may run independently for synchronous....” has been changed to “...independently for
asynchronous...”
17)
18)
19)
20)
21)
22)
23)
Under the Dual Port Configuration, a section regarding Arbitration has been added
12/7
12/7
12/7
12/7
12/7
12/7
12/7
I/O Banks
I/O Banks
Under
a block diagram of the device showing the location of the I/O banks has been added.
a table showing the I/O standards has been added.
Under
Block Diagram of Channel Memory Block
Figure 6,
Figure 8,
Figure 9,
in 12/7 Rev. deleted
Block Diagram of Dual Port Channel Memory
in 12/7 Rev. deleted
Block Diagram of FIFO Channel Memory Block
in 12/7 Rev. deleted
Switching Characteristics - Parameter Values
Cluster Memory Timing Parameter Description
Over the Operating Range table added prior to the
Over the Operating Range table.
Switching Characteristics Table
24)
25)
26)
Timing parameters added to
: tMCCCD and tSCS2PT
tADDMS
The following bullets were removed from the Delta39K features in the
no fanout delays, no expander delays, no additional delay through PIM, and no routing delays.
12/7
12/7
12/7
Channel Memory Timing:
Timing Parameter added to
Timing Model
in the section:
Timing Model paragraph
The caption was also changed to read
27)
The wording of the
was changed and now includes tMCS and tMCCO.
39K100
12/7
12/7
Switching Characteristics - Parameter Descriptions
28)
29)
table added
Channel Memory Timing Parameter Values
tADDMS added to
48
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