CY2SSTV855ZXI

更新时间： 2024-01-31 15:30:48

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动器时钟
页数	文件大小	规格书
7页	133K
描述
Differential Clock Buffer/Driver

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CY2SSTV855ZXI 数据手册

CY2SSTV855

Differential Clock Buffer/Driver

Features

Functional Description

• Phase-locked loop (PLL) clock distribution for Double

Data Rate Synchronous DRAM applications

The CY2SSTV855 is a high-performance, very-low-skew,

very-low-jitter zero-delay buffer that distributes a differential

clock input pair (SSTL_2) to four differential (SSTL_2) pairs of

clock outputs and one differential pair of feedback clock

outputs. In support of low power requirements, when

power-down is HIGH, the outputs switch in phase and

frequency with the input clock. When power-down is LOW, all

outputs are disabled to a high-impedance state and the PLL is

shut down.

• 1:5 differential outputs

• External feedback pins (FBINT, FBINC) are used to

synchronize the outputs to the clock input

• SSCG: Spread Aware™ for electromagnetic

interference (EMI) reduction

• 28-pin TSSOP package

The device supports a low-frequency power-down mode.

When the input is < 20 MHz, the PLL is disabled and the

outputs are put in the Hi-Z state. When the input frequency is

> 20 MHz, the PLL and outputs are enabled.

• Conforms to JEDEC DDR specifications

When AVDD is tied to ground, the PLL is turned off and

bypassed with the input reference clock gated to the outputs.

The Cypress CY2SSTV855 is Spread Aware and supports

tracking of Spread Spectrum clock inputs to reduce EMI

Pin Configuration

Block Diagram

GND

YC0

YT0

YC0

YC3

PWRDWN

AVDD

Powerdown

and test

logic

YT3

YT0

VDDQ

GND

VDDQ

PWRDWN

FBINT

FBINC

VDDQ

FBOUTC

FBOUTT

VDDQ

YT2

YT1

YC1

CLKINT

CLKINC

VDDQ

AVDD

AGND

YT2

YC2

CLKINT

CLKINC

PLL

YT3

YC3

FBINT

FBINC

VDDQ

YT1

YC2

YC1

FBOUTT

FBOUTC

GND

28-pin TSSOP

Cypress Semiconductor Corporation

Document #: 38-07459 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 2, 2006

12 3 4 5 6 7

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