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CY2SSTV8575ACT PDF预览

CY2SSTV8575ACT

更新时间: 2024-01-27 00:10:17
品牌 Logo 应用领域
SPECTRALINEAR 驱动器逻辑集成电路电视时钟
页数 文件大小 规格书
7页 135K
描述
Differential Clock Buffer/Driver

CY2SSTV8575ACT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP,
针数:32Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.47
系列:SSTV输入调节:DIFFERENTIAL
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:OTHER端子面层:MATTE TIN (800)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mm最小 fmax:170 MHz
Base Number Matches:1

CY2SSTV8575ACT 数据手册

 浏览型号CY2SSTV8575ACT的Datasheet PDF文件第2页浏览型号CY2SSTV8575ACT的Datasheet PDF文件第3页浏览型号CY2SSTV8575ACT的Datasheet PDF文件第4页浏览型号CY2SSTV8575ACT的Datasheet PDF文件第5页浏览型号CY2SSTV8575ACT的Datasheet PDF文件第6页浏览型号CY2SSTV8575ACT的Datasheet PDF文件第7页 
CY2SSTV8575  
Differential Clock Buffer/Driver  
Description  
Features  
• Operating frequency: 60 MHz to 170 MHz  
• Supports 266 MHz DDR SDRAM  
• 5 differential outputs from 1 differential input  
• Spread Spectrum compatible  
The CY2SSTV8575 is a high-performance, low-skew, low jitter  
zero-delay buffer designed to distribute differential clocks in  
high-speed applications. The CY2SSTV8575 generates five  
differential pair clock outputs from one differential pair clock  
input. In addition, the CY2SSTV8575 features differential  
feedback clock outputs and inputs. This allows the  
CY2SSTV8575 to be used as a zero-delay buffer.  
• Low jitter (cycle-to-cycle): < 75  
• Very low skew: < 100 ps  
When used as a zero-delay buffer in nested clock trees, the  
CY2SSTV8575 locks onto the input reference and translates  
with near zero delay to low-skew outputs.  
• Power Management Control input  
• High-impedance outputs when input clock < 20 MHz  
• 2.5V operation  
• 32-pin TQFP JEDEC MS-026 C  
Pin Configuration  
Block Diagram  
2
Y0  
Y0#  
1
12  
Y1  
Y1#  
23  
Test and  
Powerdown  
Logic  
11  
OE  
24 23 22 21 20 19 18 17  
15  
16  
8
Y2  
Y2#  
AVDD  
VSS  
VDDQ  
Y3  
Y2#  
Y2  
27  
28  
Y3  
Y3#  
30  
31  
VSS  
Y4  
Y4#  
Y3#  
VDDQ  
CY2SSTV8575  
18  
19  
FBOUT  
FBOUT#  
VDDQ  
Y4  
Y1  
Y1#  
5
6
TQFP-32  
CLK  
CLK#  
Y4#  
VSS  
JEDEC MS-026 C  
VSS  
AVSS  
PLL  
FBIN  
FBI  
#
21  
22  
1
2 3 4 5 6 7 8  
N
Rev 1.0, November 25, 2006  
2200 Laurelwood Road, Santa Clara, CA 95054  
Page 1 of 7  
www.SpectraLinear.com  
Tel:(408) 855-0555 Fax:(408) 855-0550  

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