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CY2AVC16835ZI

更新时间： 2024-09-30 15:30:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 103K
描述
Bus Driver, 1-Func, 18-Bit, True Output, PDSO56, 6 X 12 MM, TSSOP2-56

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CY2AVC16835ZI 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknown风险等级：5.84
JESD-30 代码：R-PDSO-G56长度：14 mm
逻辑集成电路类型：BUS DRIVER位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：7.8 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

CY2AVC16835ZI 数据手册

 浏览型号CY2AVC16835ZI的Datasheet PDF文件第2页浏览型号CY2AVC16835ZI的Datasheet PDF文件第3页浏览型号CY2AVC16835ZI的Datasheet PDF文件第4页浏览型号CY2AVC16835ZI的Datasheet PDF文件第5页浏览型号CY2AVC16835ZI的Datasheet PDF文件第6页浏览型号CY2AVC16835ZI的Datasheet PDF文件第7页 
CY2AVC16835  
18-Bit Universal Bus/Driver with Three-State Outputs  
Features  
Description  
• Lessthan2.8-nSmaximuminputtooutputdelayat 3.3V.  
• Wide supply voltage range of 1.2V to 3.6 V  
• Over voltage- tolerant inputs/outputs allow  
mixed-voltage-mode data communications  
• Output circuitry with VOI™ control minimizes  
over/undershoot and maximizes output drive  
• Configurable as latch or register  
• Extended temp range of –40° to + 85° C  
• 2KV ESD  
The CY2AVC16835 is a high performance, low voltage 18-bit  
universal bus driver. It is operational from 1.2V to 3.6V VDD  
,
but is designed specifically for 1.5V to 3.6V VDD operation.  
Data flow from A to Y is controlled by the output-enable (OE).  
The device operates in the transparent mode when the  
latch-enable (LE) input is high. The A data is latched if the  
clock (CLK) input is held at a high or low logic level. If LE is  
low, the A data is stored in the latch/flip-flop on the low-to-high  
transition of CLK. When OE is high, the outputs are in the  
high-impedance state.  
• 56-pin TSSOP package  
To ensure the high-impedance state during power up or power  
down, OE should be tied VDD through a pullup resistor; the  
minimum value of the resistor is determined by the  
current-sinking capability of the OE driving device.  
The output circuitry is dynamically controlled via Variable  
Output Impedance (VOI), which, during output transitions,  
initially lowers the output impedance to effectively drive the  
load and, subsequently, raises the impedance to reduce noise.  
Figure 1 shows typical VOL vs. IOL and VOH vs IOH curves  
to illustrate the output impedance and drive capability of the  
circuit.  
Block Diagram  
Pin Configuration  
NC  
NC  
Y1  
VSS  
Y2  
Y3  
VDD  
Y4  
Y5  
Y6  
VSS  
Y7  
VSS  
NC  
A1  
VSS  
A2  
A3  
VDD  
A4  
A5  
A6  
VSS  
A7  
1
2
3
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
4
5
6
7
8
9
27  
OE  
30  
CLK  
28  
LE  
54  
A1  
D
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
3
LE  
CLK  
Y1  
Y8  
Y9  
A8  
A9  
Y10  
Y11  
Y12  
VSS  
Y13  
Y14  
Y15  
VDD  
Y16  
Y17  
VSS  
Y18  
OE  
LE  
A10  
A11  
A12  
VSS  
A13  
A14  
A15  
VDD  
A16  
A17  
VSS  
A18  
CLK  
VSS  
To 17 Other Channels  
Cypress Semiconductor Corporation  
Document #: 38-07462 Rev. *A  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised April 16, 2003  
1234567...10

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