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CY27C256-150JC PDF预览

CY27C256-150JC

更新时间： 2024-01-31 19:51:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路可编程只读存储器OTP只读存储器电动程控只读存储器
页数 文件大小 规格书
11页 264K
描述
32K x 8-Bit CMOS EPROM

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CY27C256-150JC 技术参数

生命周期：Obsolete零件包装代码：TSOP
包装说明：SOP,针数：32
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.83
最长访问时间：150 nsJESD-30 代码：R-PDSO-G32
JESD-609代码：e0内存密度：262144 bit
内存集成电路类型：OTP ROM内存宽度：8
功能数量：1端子数量：32
字数：32768 words字数代码：32000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：32KX8
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
认证状态：Not Qualified最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子位置：DUAL

CY27C256-150JC 数据手册

 浏览型号CY27C256-150JC的Datasheet PDF文件第2页浏览型号CY27C256-150JC的Datasheet PDF文件第3页浏览型号CY27C256-150JC的Datasheet PDF文件第4页浏览型号CY27C256-150JC的Datasheet PDF文件第5页浏览型号CY27C256-150JC的Datasheet PDF文件第6页浏览型号CY27C256-150JC的Datasheet PDF文件第7页 
1CY27C256  
fax id: 3013  
CY27C256  
32K x 8-Bit CMOS EPROM  
able in a CerDIP package equipped with an erasure window  
to provide for reprogrammability. When exposed to UV light,  
the EPROM is erased and can be reprogrammed. The mem-  
ory cells utilize proven EPROM floating gate technology and  
byte-wide intelligent programming algorithms.  
Features  
• Wide speed range  
— 45 ns to 200 ns (commercial and military)  
• Low power  
The CY27C256 offers the advantage of lower power and su-  
perior performance and programming yield. The EPROM cell  
requires only 12.5V for the super voltage, and low current re-  
quirements allow for gang programming. The EPROM cells  
allow each memory location to be tested 100% because each  
location is written into, erased, and repeatedly exercised prior  
to encapsulation. Each EPROM is also tested for AC perfor-  
mance to guarantee that after customer programming, the  
product will meet both DC and AC specification limits.  
— 248 mW (commercial)  
— 303 mW (military)  
• Low standby power  
— Less than 83 mW when deselected  
• ±10% Power supply tolerance  
Functional Description  
Reading the CY27C256 is accomplished by placing active  
LOW signals on OE and CE. The contents of the memory location  
addressed by the address lines (A - A ) will become available on  
The CY27C256 is a high-performance 32,768-word by 8-bit  
CMOS EPROM. When disabled (CE HIGH), the CY27C256  
automatically powers down into a low-power stand-by mode.  
The CY27C256 is packaged in the industry standard 600-mil  
DIP, PLCC, and TSOP packages. The CY27C256 is also avail-  
0
14  
the output lines (O - O ).  
0
7
Pin Configurations  
Logic Block Diagram  
O
7
A
14  
A
A
13  
DIP/Flatpack  
[1]  
LCC/PLCC  
12  
O
6
256 x 1024  
PROGRAMABLE  
ARRAY  
V
1
28  
V
PP  
CC  
ROW  
8 x 1 OF 128  
MULTIPLEXER  
A
11  
A
10  
ADDRESS  
A
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
27  
26  
A
12  
14  
4
3 2 323130  
1
A
A
8
A
13  
7
29  
A
6
5
6
7
8
9
10  
11  
12  
13  
O
5
A
9
A
A
6
A
A
9
28  
27  
26  
25  
24  
23  
22  
21  
25  
24  
5
8
27C256  
A
11  
A
A
4
A
3
A
A
5
8
9
NC  
OE  
27C256  
A
A
11  
23  
22  
21  
A
4
7
A
2
ADDRESS  
DECODER  
O
4
A
3
A
OE  
A
A
10  
A
1
6
A
CE  
A
2
0
10  
A
O
5
NC  
O
7
A
1
CE  
20  
19  
18  
17  
16  
O
6
0
A
4
A
0
O
3
O
7
O
14151617 181920  
O
A
0
6
3
COLUMN  
ADDRESS  
O
1
O
5
A
2
27c256–3  
O
2
O
O
3
4
O
2
A
GND  
15  
1
27c256–2  
A
0
O
1
POWER–DOWN  
O
0
CE  
OE  
27c256–1  
Note:  
1. For PLCC only: Pins 1 and 17 are common and tied to the die attach pad. They must therefore be DU (don’t use) for the PLCC package.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
May 1993 – Revised August 1994  
•
408-943-2600  
1234567...11

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