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CY25403SXCT PDF预览

CY25403SXCT

更新时间: 2024-10-01 09:41:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
14页 245K
描述
Three PLL Programmable Clock Generator with Spread Spectrum

CY25403SXCT 数据手册

 浏览型号CY25403SXCT的Datasheet PDF文件第2页浏览型号CY25403SXCT的Datasheet PDF文件第3页浏览型号CY25403SXCT的Datasheet PDF文件第4页浏览型号CY25403SXCT的Datasheet PDF文件第5页浏览型号CY25403SXCT的Datasheet PDF文件第6页浏览型号CY25403SXCT的Datasheet PDF文件第7页 
CY25403/CY25423/CY25483  
Three PLL Programmable Clock Generator  
with Spread Spectrum  
Features  
Three fully integrated phase-locked loops (PLLs)  
Three clock outputs with programmable drive strength  
Glitch-free outputs while frequency switching  
8-pin SOIC package  
Input frequency range  
External crystal: 8 to 48 MHz  
External reference: 8 to 166 MHz clock  
Commercial and Industrial temperature ranges  
Reference clock input voltage range  
1.8 V for CY25403/CY25423/CY25483  
Benefits  
Wide operating output frequency range  
3 to 166 MHz  
Multiple high performance PLLs allow synthesis of unrelated  
frequencies  
Programmable spread spectrum with center and down spread  
option and lexmark and linear modulation profiles  
Nonvolatile programming for personalization of PLL  
frequencies, spread spectrum characteristics, drive strength,  
crystal load capacitance, and output frequencies  
VDD supply voltage options:  
2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483  
ApplicationspecificprogrammableEMIreductionusingSpread  
Spectrum for clocks  
Selectable output clock voltages independent of VDD supply:  
2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483  
Programmable PLLs for system frequency margin tests  
Frequency select feature with option to select four different  
frequencies  
Meets critical timing requirements in complex system designs  
Suitability for PC, consumer, portable, and networking  
applications  
Power-down, output enable, and SS ON/OFF controls  
Low jitter, high accuracy outputs  
Capable of Zero PPM frequency synthesis error  
AbilitytosynthesizenonstandardfrequencieswithFractional-N  
capability  
Uninterrupted system operation during clock frequency switch  
Application compatibility in standard and low power systems  
Block Diagram  
Crossbar  
Switch  
XIN/  
EXCLKIN  
CLK1  
(SS)  
Output  
OSC  
PLL1  
XOUT  
Dividers  
and  
MUX  
and  
CLK2  
(No SS)  
Drive  
PLL 2  
(SS)  
FS0  
FS1  
Strength  
Control  
Control  
Logic  
CLK3  
(SS)  
PLL3  
(SS)  
SSON  
PD#/OE  
Cypress Semiconductor Corporation  
Document #: 001-12564 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 18, 2011  

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