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CY25403SXC-XXXT PDF预览

CY25403SXC-XXXT

更新时间: 2024-10-01 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器
页数 文件大小 规格书
8页 260K
描述
Three PLL Programmable Clock Generator with Spread Spectrum

CY25403SXC-XXXT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.18
其他特性:IT CAN ALSO OPERATES ON 3 OR 3.3 V SUPPLYJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.889 mm
湿度敏感等级:3端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:166 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
主时钟/晶体标称频率:48 MHz认证状态:Not Qualified
座面最大高度:1.727 mm子类别:Clock Generators
最大供电电压:3.6 V最小供电电压:2.25 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:3.8985 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY25403SXC-XXXT 数据手册

 浏览型号CY25403SXC-XXXT的Datasheet PDF文件第2页浏览型号CY25403SXC-XXXT的Datasheet PDF文件第3页浏览型号CY25403SXC-XXXT的Datasheet PDF文件第4页浏览型号CY25403SXC-XXXT的Datasheet PDF文件第5页浏览型号CY25403SXC-XXXT的Datasheet PDF文件第6页浏览型号CY25403SXC-XXXT的Datasheet PDF文件第7页 
CY25403  
CY25423  
PRELIMINARY  
Three PLL Programmable Clock Generator  
with Spread Spectrum  
Features  
Benefits  
• Three fully integrated phase-locked loops (PLLs)  
• Input Frequency range:  
• Multiple high-performance PLLs allow synthesis of  
unrelated frequencies  
• Nonvolatile programming for customized PLL frequencies,  
spreadspectrumcharacteristics, drivestrength,crystalload  
capacitance, and output frequencies  
— External crystal: 8 to 48 MHz  
— External reference: 8 to 166 MHz clock  
• Wide operating output frequency range  
— 3 to 166 MHz  
• Two Spread Spectrum capable PLLs with Lexmark profile  
for maximum for EMI reduction  
• Spread Spectrum PLLs can be disabled or enabled  
separately  
• Programmable Spread Spectrum modulation frequency  
range of 30 to 120 kHz with Lexmark profile  
• PLLs can be programmed for system frequency margin  
tests  
• Center Spread: ±0.125% to ±2.5%  
• Down Spread: –0.25% to –5%  
• Meets critical timing requirements in complex system  
designs  
• Frequency select feature with option to select four different  
frequencies  
• Suitable for PC, consumer, and networking applications  
• Ability to synthesize standard frequencies with ease  
• Low-jitter, high-accuracy outputs  
• Up to three clock outputs  
• Application compatibility in standard and low-power  
systems  
• Programmable output drive strength  
• Glitch-free outputs while frequency switching  
• Four independent output voltages: 3.3V, 3.0V, 2.5V, and  
1.8V  
• 8-pin SOIC package  
• Commercial and Industrial temperature range  
Block Diagram  
3 of 4  
Crossbar  
Switch  
XIN  
OSC  
PLL1  
XOUT  
Output  
CLK1  
Dividers  
and  
Drive  
Strength  
Control  
CLK2  
CLK3  
MUX  
and  
Control  
Logic  
PLL2  
(SS)  
FS0  
FS1  
PLL3  
(SS)  
SSON  
PD#/OE  
Cypress Semiconductor Corporation  
Document #: 001-12564 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 02, 2007  
[+] Feedback  

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