PRELIMINARY
CY241V08A-02
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883.................> 2000V
Absolute Maximum Conditions
Supply Voltage (VDD)........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-condensing).....–55°C to +125°C
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Junction Temperature ................................ –40°C to +125°C
Pullable Crystal Specifications[1]
Parameter
Description
Comments
Min. Typ. Max. Unit
FNOM
Nominal crystal frequency
Parallel resonance, fundamental mode, AT
–
27
–
MHz
cut
CLNOM
R1
R3/R1
Nominal load capacitance
Equivalent series resistance (ESR)
–
–
3
14
–
–
–
25
–
pF
Ω
–
Fundamental mode
Ratio of third overtone mode ESR to
Ratio used because typical R1 values are
fundamental mode ESR
much less than the maximum spec
DL
Crystal drive level
No external series resistor assumed
150
300
–
–
180
–
–
–
–
–
–
–
µW
ppm
F3SEPHI
F3SEPLO
C0
C0/C1
C1
Third overtone separation from 3*FNOM High side
Third overtone separation from 3*FNOM Low side
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
–150 ppm
7
250
21.6
pF
–
fF
14.4 18
Recommended Operating Conditions
Parameter
Description
Min.
3.135
0
Typ.
3.3
–
Max.
3.465
70
Unit
V
°C
VDD
TA
Operating Voltage
Ambient Temperature
CLOAD
tPU
Max. Load Capacitance
–
0.05
–
–
15
500
pF
ms
Power-up timefor allVDD pinstoreachminimum specified
voltage (power ramps must be monotonic)
DC Electrical Specifications
Parameter
IOH
IOL
CIN
Name
Description
VOH = VDD – 0.5V, VDD = 3.3V
VOL = 0.5V, VDD = 3.3V
Min.
Typ.
24
24
–
Max.
Unit
mA
mA
pF
Output HIGH Current
Output LOW Current
Input Capacitance
12
12
–
–
–
7
Except XIN, XOUT pins
VVCXO
f∆XO
VCXO Input Range
VCXO Pullability Range
0
–
115
–
–
–
–
–
VDD
–115
–
V
[2]
Low Side
High Side
ppm
ppm
mA
IVDD
Supply Current
35
AC Electrical Specifications (VDD = 3.3V) [3]
Parameter[3]
DC
ER
Name
Output Duty Cycle
Rising Edge Rate
Description
Duty Cycle is defined in Figure 1, 50% of VDD
Min.
45
0.8
Typ. Max. Unit
50
55
%
Output Clock Edge Rate, Measured from 20%
1.4
–
V/ns
to 80% of VDD, CLOAD = 15 pF. See Figure 2.
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
0.8
–
1.4
–
–
V/ns
ps
to 20% of VDD, CLOAD = 15 pF. See Figure 2.
t9
Peak-to-peak Period Jitter
27-MHz Clock Jitter
100
Notes:
1. Crystals that meet this specification includes: Ecliptek ECX-5808-27.000M
2. –115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less
board capacitance.
3. Not 100% tested.
Document #: 38-07674 Rev. *A
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