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CY2292ASL-XXXT PDF预览

CY2292ASL-XXXT

更新时间: 2024-11-23 21:20:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 110K
描述
Processor Specific Clock Generator, 80MHz, CMOS, PDSO16, 0.150 INCH, PLASTIC, SOIC-16

CY2292ASL-XXXT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.75
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.8933 mm湿度敏感等级:1
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:80 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:30 MHz
认证状态:Not Qualified座面最大高度:1.7272 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:3.8989 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CY2292ASL-XXXT 数据手册

 浏览型号CY2292ASL-XXXT的Datasheet PDF文件第2页浏览型号CY2292ASL-XXXT的Datasheet PDF文件第3页浏览型号CY2292ASL-XXXT的Datasheet PDF文件第4页浏览型号CY2292ASL-XXXT的Datasheet PDF文件第5页浏览型号CY2292ASL-XXXT的Datasheet PDF文件第6页浏览型号CY2292ASL-XXXT的Datasheet PDF文件第7页 
CY2292A  
Three-PLL General Purpose  
EPROM Programmable Clock Generator  
Features  
Three integrated phase-locked loops  
EPROM programmability  
Benefits  
Generates up to 3 custom frequencies from external sources  
Easy customization and fast turnaround  
Factory-programmable  
Programming support available for all opportunities  
Meets critical industry-standard timing requirements  
Low-skew, low-jitter, high-accuracy outputs  
Power-management options (Shutdown, OE, Suspend)  
Frequency select option  
Supports low-power applications  
8 user-selectable frequencies on CPU PLL  
Allows downstream PLLs to stay locked on CPUCLK output  
Enables application compatibility  
Smooth slewing on CPUCLK  
Configurable 3.3V or 5V operation  
16-pin SOIC Package (TSSOP: F only)  
Industry-standard packaging saves on board space  
Selector Guide  
Part Number Outputs  
CY2292A  
Input Frequency Range  
Output Frequency Range  
Specifics  
6
10 MHz–25 MHz (external crystal) 76.923 kHz–100 MHz (5V)  
1 MHz–30 MHz (reference clock) 76.923 kHz–80 MHz (3.3V)  
Factory Programmable  
Commercial Temperature  
Logic Block Diagram  
.
XTALIN  
OSC.  
XBUF  
CPUCLK  
CLKA  
XTALOUT  
CPLL  
(8 BIT)  
/1,2,4  
S0  
S1  
S2/SUSPEND  
UPLL  
(10 BIT)  
CLKB  
/1,2,4,8  
CLKC  
CLKD  
/1,2,3,4,5,6  
/8,10,12,13  
/20,24,26,40  
/48,52,96,104  
SPLL  
(8 BIT)  
CONFIG  
EPROM  
SHUTDOWN/  
OE  
Pin Configurations  
CY2292A  
16-pin SOIC  
CLKC  
SHUTDOWN/OE  
S2/SUSPEND  
1
2
3
4
5
6
16  
15  
14  
13  
12  
V
DD  
GND  
V
DD  
XTALIN  
XTALOUT  
XBUF  
S1  
S0  
11  
10  
GND  
CLKD  
CLKA  
CLKB  
7
8
9
CPUCLK  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
September 5, 2000  

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