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CY22801

更新时间: 2024-11-25 04:37:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器PC
页数 文件大小 规格书
7页 255K
描述
Universal Programmable Clock Generator (UPCG)

CY22801 数据手册

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CY22801  
Universal Programmable Clock  
Generator (UPCG)  
Benefits  
Features  
• Integrated phase-locked loop (PLL)  
• Field programmable  
• Inventory of only one device, CY22801, is needed to use in  
various applications  
• In-house programming of samples and prototype quantities  
is available using the CY36800 InstaClock Kit  
• Input frequency range:  
— Crystal: 8–30 MHz  
• Can customize the input and output frequencies to suit your  
needs  
— CLKIN: 1–133 MHz  
• Output frequency:  
• High-performance PLL tailored for multiple applications  
— LVCMOS: 1–200 MHz  
• Low jitter, high accuracy outputs  
• 3.3V operation  
• Meets critical timing requirements in complex system  
designs  
• Enables application compatibility  
• 8-pin SOIC package  
Logic Block Diagram  
Pin Configuration  
CY22801  
8-pin SOIC  
CLKA  
CLKB  
CLKC  
XIN/CLKIN  
XTAL  
XOUT  
1
OUTPUT  
DIVIDERS  
XIN/CLKIN  
8
PLL  
OSC  
2
3
4
7
6
5
CLKC  
CLKA  
CLKB  
VDD  
NC  
XOUT  
VSS  
Pin Description  
Name  
XIN  
Pin Number Description  
1
2
3
4
5
6
7
8
Reference Input: Crystal or External Clock  
3.3V Voltage Supply  
No Connect; leave this pin floating  
Ground  
VDD  
NC  
VSS  
CLKB  
CLKA  
CLKC  
XOUT  
Clock Output B  
Clock Output A  
Clock Output C  
Reference Output: Connect to external crystal. When the reference is an external clock  
signal, this pin is not used and must be left floating.  
Cypress Semiconductor Corporation  
Document #: 001-15571 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 10, 2007  
[+] Feedback  

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