CXD2458AR

更新时间： 2024-01-07 06:11:50

品牌	Logo	应用领域
索尼 - SONY		消费电路商用集成电路
页数	文件大小	规格书
56页	1553K
描述
Timing Generator for Color LCD Panels

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技术参数
数据手册

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CXD2458AR 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	48
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-PQFP-G48
长度：	7 mm	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.85 mm	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	7 mm
Base Number Matches：	1

CXD2458AR 数据手册

CXD2458AR

AFC Circuit (PLL Method)

The CXD2458AR employs the PLL method in order to achieve phase synchronization with the input sync

signal.

The PLL circuit phase comparator and frequency division counter are built in, and a fully synchronized AFC

circuit is comprised by connecting an external VCO circuit and LPF.

PLL errors are detected at the following timing.

The phase comparison output of the entire bottom of XHD or the horizontal sync signal of composite SYNC

and the internal H counter becomes RPD. RPD output is converted to DC error with the lag-lead filter (LPF),

and then it changes the varicap capacitance to stabilize the oscillating frequency at 702fh in the

LCX005BK/BKB and LCX024AK, and 1050fh in the LCX009AK/AKB and LCX027AK.

This PLL circuit is adjusted by setting the RPD transition point so that it sets in the center of the window (XHD

or horizontal sync signal of composite SYNC) as shown in the figure below.

4.7µs

XHD or horizontal sync signal of

composite SYNC

RPD

WL = WH

AC Driving for No Signal

HST1/2, HCK1/2, FRP, VCK1/2, XCLP, VST, HD, VD, SH1/2/3/4 and EN are made to run freely so that the

LCD panel is AC driven even when there are no input sync signals (XHD/XVD and composite SYNC).

During this time, the horizontal sync separation circuit stops and the PLL internal frequency division counter is

made to run freely. At the same time, the auxiliary V counter is used to create the reference pulse for

generating the free running VD and VST because the vertical sync separation circuit is also stopped.

The cycle of this V counter is set to 269H for NTSC and 321H for PAL. However, when there is no XVD

(VSYNC) input for 301H (NTSC) and 360H (PAL), the no signal state is assumed and the free running VD and

VST pulses are generated from the next field.

RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing phase

errors due to phase comparison.

System Clear (XCLR)

The entire logic is initialized by setting XCLR = L. Be sure to perform this operation during power-on and after

changing the STBY pin from L to H. When this function is activated the outputs (XCLP, HD, FRP, VST, VD,

CLR, EN, HST1/2, HCK1/2, SH1/2/3/4, VCK1/2, FLDO, SBLK and BLK) go to L.

– 10 –

1...7 8 91011 12 13...56

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