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CXD2508AQ PDF预览

CXD2508AQ

更新时间: 2024-01-25 19:40:37
品牌 Logo 应用领域
索尼 - SONY 数字信号处理器
页数 文件大小 规格书
49页 856K
描述
CD Digital Signal Processor

CXD2508AQ 数据手册

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CXD2508AQ/AR  
CD Digital Signal Processor  
For the availability of this product, please contact the sales office.  
Description  
CXD2508AQ  
80 pin QFP (Plastic)  
CXD2508AQ  
80 pin QFP (Plastic)  
The CXD2508AQ/AR is a digital signal processor  
for CD players and is equipped with built-in digital  
filters, no-sound data detection circuit, and 1-bit  
DAC.  
Features  
DSP block  
Digital PLL  
EFM frame sync protection  
SEC strategy-based error correction  
Subcode demodulation, CRC checking  
Digital spindle servo  
CXD2508AR  
80 pin LQFP (Plastic)  
CXD2508AQ  
80 pin QFP (Plastic)  
Servo auto sequencer  
Asymmetry compensation circuit  
Digital audio interface output  
16K RAM  
Double-speed playback capability  
New microcomputer interface circuit  
Digital filter, DAC block  
Double-speed playback capability  
Digital de-emphasis  
Digital attenuation  
Applications  
CD players  
No-sound data detection circuit  
4 Fs oversampling filter  
Secondary ∆∑ noise shaper  
PWM-system pulse conversion output  
Structure  
Silicon gate CMOS IC  
Absolute Maximum Ratings  
Supply voltage VDD  
–0.3 to 7.0  
–0.3 to 7.0  
V
V
Recommended Operating Conditions  
Input voltage  
Input voltage  
VI  
Note)  
Supply voltage VDD  
4.5 to 5.5V  
VIN Vss–0.3V (min.) VDD+0.3 (max.) V  
(double-speed playback)  
3.5 to 5.5V  
(normal-speed playback)  
3.4 to 5.5V  
(low power consumption  
or special playback mode)  
Output voltage VO  
Storage temperature  
Tstg  
–0.3 to 7.0  
V
–40 to 125  
°C  
Supply voltage variation  
V
SS–AVSS –0.3V (min.) +0.3V (max.)  
DD–AVDD –0.3V (min.) +0.3V (max.)  
V
Operating temperature  
Topr  
–20 (min.) 75 (max.)  
°C  
Note) VDD (min.) is varied by the playback speed and built-in  
VCO in the CXD2508AQ/AR. 4.5V is the value using the  
VCO which generates the slower frequency in double-  
speed playback. The table below shows the VDD (min.)  
for each condition.  
VDD (min.) [V]  
Playback  
VCO  
VCO  
speed  
DAC block  
high-speed normal-speed  
× 2  
3.40  
3.40  
3.40  
4.50  
3.50  
3.40  
3.40  
3.40  
3.40  
× 1  
× 1  
When the internal operation of the LSI is set to double-  
speed mode and the crystal oscillation frequency is  
halved, normal-speed playback results.  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E94602A54-ST  

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