CPVDD
CPVSS
CPFLYBCK1
CPFLYBCK2
CPVOUTP
CPVOUTN
VDDIO1
VDDIO2
VSSIO1
VSSIO2
MCLK1
C8
B8
D8
D9
E8
E9
F9
H3
F8
H2
F4
F7
F6
F5
analog
analog
analog
analog
analog
analog
power
power
power
power
pd_gpio
pd_gpio
pd_gpio
pd_gpio
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
Charge-pump Supply
Charge-pump Supply
Flyback capacitor
Flyback capacitor
Charge-pump DC-DC supply.
Charge-pump DC-DC supply.
Pad Ring Pwr. GPIO/I2S/I2S-pass-thru, & I2S/CAB/Host/Ctrl
Pad Ring Pwr. GPIO/I2S/I2S-pass-thru, & I2S/CAB/Host/Ctrl
Pad Ring Gnd. 3.3V nominal. 3 sets for VSSIO.
Pad Ring Gnd. 3.3V nominal. 3 sets for VSSIO.
Master Reference Clocks for PLLs. (MCLK2 = GPIO[3])
Master Reference Clocks for PLLs. (MCLK2 = GPIO[3])
5-b General purpose I/O port.
MCLK2/GPIO3
GPIO2
GPIO1
I
I/O
I/O
5-b General purpose I/O port. MCLK2 and HSS are alternative
general purpose I/O ports.
GPIO0
H1
pd_gpio
I/O
5-b General purpose I/O port. MCLK2 and HSS are alternative
general purpose I/O ports.
HSCLK
HSIMO
HSOMI
F3
F1
F2
pd_gpio
pd_gpin
pd_gpio
I
I
Serial Clock (or SCL)
Serial Data input (alt_slave_id)
Slave Output (or SDA)
I/O
TERMINAL
BALL
INPUT/
OUTPUT/
POWER
DESCRIPTION
NAME
TYPE
WCSP
(I/O/P)
P
LDO2VDD
E1
power
LDO input power
I/O
I
I/O
I
HSS/GPIO4
HIM
AIF{1,2,A}_BCLK
AIF{1,2,A}_RXD
AIF{1,2,A}_TXD
G9
G8
G{8,6,5}
G{4,3,2}
G{1},
pd_gpio
pd_gpio
pd_gpio
pd_gpin
pd_gpio
Slave select (or GPIO[4])
Host Interface Mode, 1 = SPI, 0 = I2C
I2S/PCM Bit Clock (AIF2_BCLK = C_CLK)
Receive Data (AIF2_RXD = C_DI,AIF1_RXD=C_RST)
Transmit Data (AIF2_TXD = C_DO)
O
H{9,8}
H{7,6,5]
I/O
AIF{1,2,A}_WS
pd_gpio
Receive/Transmit Word Select (AIF2_WS = C_FRM