Datasheet > CSTLS8M38G53

CSTLS8M38G53

更新时间： 2022-11-25 18:31:23

品牌	Logo	应用领域
日电电子 - NEC		微控制器
页数	文件大小	规格书
592页	3187K
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8-Bit Single-Chip Microcontrollers

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CSTLS8M38G53 数据手册

APPENDIX E REVISION HISTORY

E.2 Revision History up to Previous Edition

The history of revisions made up to this edition is shown below.

(1/4)

Edition

2nd

Contents

Applied to:

Throughout

Addition of the following package

• 64-pin plastic LQFP (GC-8BS type)

Addition of expanded-specification products to the µPD780078 Subseries

Addition of 1.1 Expanded-Specification Products and Conventional Products

CHAPTER 1 OUTLINE

(µPD780078 SUBSERIES)

Modification of voltage operation range of A/D converter in 1.8 Outline of

Functions

Modification of voltage operation range of A/D converter in 2.7 Outline of

CHAPTER 2 OUTLINE

(µPD780078Y

Functions

SUBSERIES)

Addition of description about pin processing in 3.2.17 VPP (flash memory version

CHAPTER 3 PIN

FUNCTION (µPD780078

SUBSERIES)

only)

Modification of I/O circuit types of P32 and P33 in Table 3-1 Pin I/O Circuit

Types

Addition of description about pin processing in 4.2.17 VPP (flash memory version

CHAPTER 4 PIN

only)

FUNCTION (µPD780078Y

SUBSERIES)

Addition of description about programming area in 5.1.2 (1) Internal high-speed

RAM and (2) Internal expansion RAM

CHAPTER 5 CPU

ARCHITECTURE

Modification of Figure 5-10 Data to Be Saved to Stack Memory and Figure 5-11

Data to Be Restored from Stack Memory

Modification of [Description example] in 5.4.4 Short direct addressing

Addition of [Illustration] in 5.4.7 Based addressing, 5.4.8 Based indexed

addressing, and 5.4.9 Stack addressing

Modification of port block diagrams (Figure 6-2 Block Diagram of P00 to P03 to

Figure 6-21 Block Diagram of P80)

CHAPTER 6 PORT

FUNCTIONS

Addition of Table 6-6 Port Mode Registers and Output Latch Setting When

Alternate Function Is Used

Addition of description of internal feedback resistor and oscillation stabilization

CHAPTER 7 CLOCK

GENERATOR

time select register (OSTS) in 7.3 Clock Generator Control Register

Deletion of 8.5.6 One-shot pulse output operation in the previous edition

CHAPTER 8 16-BIT

TIMER/EVENT

Modification of Figure 8-1 Block Diagram of 16-Bit Timer/Event Counter 00

and Figure 8-2 Block Diagram of 16-Bit Timer/Event Counter 01

COUNTERS 00, 01

Change of Table 8-2 TI00n Pin Valid Edge and CR00n, CR01n Capture Trigger

and Table 8-3 TI01n Pin Valid Edge and CR00n Capture Trigger in the

previous edition to Table 8-2 CR00n Capture Trigger and Valid Edges of TI00n

and TI01n Pins and Table 8-3 CR01n Capture Trigger and Valid Edge of TI00n

Pin (CRC02n = 1)

Change of explanation order of each function in 8.4 Operation of 16-Bit Timer/

Event Counters 00, 01

Addition of Figure 8-31 PPG Output Configuration Diagram and Figure 8-32

PPG Output Operation Timing

User’s Manual U14260EJ3V1UD

589

1...586 587 588589590 591 592

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与CSTLS8M38G53相关器件

型号	品牌	获取价格	描述	数据表
CSTLS8M38G53-A0	MURATA	获取价格	cost-effective and reliable availability
CSTLS8M38G53-B0	MURATA	获取价格	cost-effective and reliable availability
CSTLS8M38G53Z-B0	MURATA	获取价格	cost-effective and reliable availability
CSTLS8M38G56-A0	MURATA	获取价格	cost-effective and reliable availability
CSTLS8M38G56-B0	MURATA	获取价格	cost-effective and reliable availability
CSTLS8M38G56Z-B0	MURATA	获取价格	cost-effective and reliable availability
CSTLS8M50G56-B0	MURATA	获取价格	cost-effective and reliable availability
CSTLS8M50G56Z-B0	MURATA	获取价格	cost-effective and reliable availability
CSTLS9M00G53-B0	MURATA	获取价格	cost-effective and reliable availability
CSTLS9M00G56-B0	MURATA	获取价格	cost-effective and reliable availability

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