CS4329-KS

更新时间： 2024-02-08 06:42:25

品牌	Logo	应用领域
凌云 - CIRRUS		转换器光电二极管
页数	文件大小	规格书
36页	1538K
描述
20-Bit, Stereo D/A Converter for Digital Audio

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中文翻译

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技术参数
数据手册

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CS4329-KS 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	20
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	最大模拟输出电压：	2.1 V
最小模拟输出电压：	1.9 V	转换器类型：	D/A CONVERTER
输入位码：	2'S COMPLEMENT	输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e0
长度：	7.2 mm	位数：	20
功能数量：	1	端子数量：	20
最高工作温度：	70 °C	最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	COMMERCIAL
座面最大高度：	2.13 mm	标称供电电压：	5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5.3 mm
Base Number Matches：	1

CS4329-KS 数据手册

CS4329

in 2's-complement format with the MSB-first in all

seven formats.

SYSTEM DESIGN

Master Clock

Formats 0, 1 and 2 are shown in Figure 3. The audio

data is right-justified, LSB aligned with the trailing

edge of LRCK, and latched into the serial input

data buffer on the rising edge of SCLK. Formats 0,

1 and 2 are 16, 18 and 20-bit versions and differ

only in the number of data bits required.

The Master Clock, MCLK, is used to operate the

digital interpolation filter and the delta-sigma mod-

ulator. MCLK must be either 256×, 384× or 512×

the desired Input Sample Rate, Fs. Fs is the fre-

quency at which digital audio samples for each

channel are input to the DAC and is equal to the

LRCK frequency. The MCLK to LRCK frequency

ratio is detected automatically during the initializa-

tion sequence by counting the number of MCLK

transitions during a single LRCK period. Internal

dividers are then set to generate the proper clocks

for the digital filter, delta-sigma modulator and

switched-capacitor filter. LRCK must be synchro-

nous with MCLK. Once the MCLK to LRCK fre-

quency ratio has been detected, the phase and

frequency relationship between the two clocks

must remain fixed. If during any LRCK this rela-

tionship is changed, the CS4329 will reset. Table 1

illustrates the standard audio sample rates and the

required MCLK frequencies.

Formats 3 and 4 are 20-bit left justified, MSB

aligned with the leading edge of LRCK, and are

identical with the exception of the SCLK edge used

to latch data. Data is latched on the falling edge of

SCLK in Format 3 and the rising edge of SCLK in

Format 4. Both formats will support 16 and 18-bit

inputs if the data is followed by four or two zeros to

simulate a 20-bit input as shown in Figures 4 and 5.

A very small offset will result if the 18 or 16-bit

data is followed by static non-zero data.

Formats 5 and 6 are compatible with the I S serial

data protocol and are shown in Figures 6 and 7. No-

tice that the MSB is delayed 1 period of SCLK fol-

lowing the leading edge of LRCK and LRCK is

inverted compared to the previous formats. Data is

latched on the rising edge of SCLK. Format 5 is 16-

(kHz)

MCLK (MHz)

384x

256x

512x

bit I S while Format 6 is 20-bit I S. 18-bit I S can

be implemented in Format 6 if the data is followed

by two zeros to simulate a 20-bit input as shown in

Figure 7. A very small offset will result if the 18-bit

data is followed by static non-zero data.

44.1

8.1920

11.2896

12.2880

16.9344

18.4320

16.3840

22.5792

24.5760

Table 1. Common Clock Frequencies

Serial Data Interface

DIF2

DIF1

DIF0

Format

Figure

The Serial Data interface is accomplished via the

serial data input, SDATA, serial data clock, SCLK,

and the left/right clock, LRCK. The CS4329 sup-

ports seven serial data formats which are selected

via the digital input format pins DIF0, DIF1 and

DIF2. The different formats control the relation-

ship of LRCK to the serial data and the edge of

SCLK used to latch the data into the input buffer.

Table 2 lists the seven formats, along with the asso-

ciated figure number. The serial data is represented

Calibrate

Table 2. Digital Input Formats

DS153F1

1...5 6 789 10 11...36

中文翻译

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与CS4329-KS相关器件

型号	品牌	获取价格	描述	数据表
CS4330	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4330-BS	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4330-KS	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4331	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4331-BS	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4331-KS	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4331-KSZ	CIRRUS	获取价格	D/A Converter, 18-Bit, 2 Func, CMOS, PDSO8
CS4333	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4333-BS	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio
CS4333-KS	CIRRUS	获取价格	8 Pin Stereo D/A Converter for Digital Audio

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