CS42L51
4.5.3 High-Impedance Digital Output ........................................................................... 38
4.5.4 Quarter- and Half-Speed Mode ........................................................................... 39
4.6 Digital Interface Formats ................................................................................................. 39
4.7 Initialization ...................................................................................................................... 40
4.8 Recommended Power-Up Sequence .............................................................................. 40
4.9 Recommended Power-Down Sequence ......................................................................... 41
4.10 Software Mode .............................................................................................................. 42
4.10.1 SPI Control ........................................................................................................ 42
4.10.2 I²C Control ......................................................................................................... 42
4.10.3 Memory Address Pointer (MAP) ....................................................................... 44
4.10.3.1 Map Increment (INCR) .......................................................................... 44
5. REGISTER QUICK REFERENCE .......................................................................................... 45
6. REGISTER DESCRIPTION .................................................................................................... 47
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ........................................... 47
6.2 Power Control 1 (Address 02h) ....................................................................................... 47
6.3 MIC Power Control & Speed Control (Address 03h) ...................................................... 48
6.4 Interface Control (Address 04h) ...................................................................................... 49
6.5 MIC Control (Address 05h) .............................................................................................. 51
6.6 ADC Control (Address 06h) ............................................................................................. 52
6.7 ADCx Input Select, Invert & Mute (Address 07h) ............................................................ 53
6.8 DAC Output Control (Address 08h) ................................................................................. 54
6.9 DAC Control (Address 09h) ............................................................................................. 55
6.10 ALCX & PGAX Control:
ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ..................................... 56
6.11 ADCx Attenuator:
ADCA (Address 0Ch) & ADCB (Address 0Dh) ............................................................ 57
6.12 ADCx Mixer Volume Control:
ADCA (Address 0Eh) & ADCB (Address 0Fh) ............................................................. 58
6.13 PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h) ............................................................. 59
6.14 Beep Frequency & Timing Configuration (Address 12h) ............................................... 60
6.15 Beep Off Time & Volume (Address 13h) ....................................................................... 61
6.16 Beep Configuration & Tone Configuration (Address 14h) ............................................. 62
6.17 Tone Control (Address 15h) .......................................................................................... 63
6.18 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h) ......................................................... 64
6.20 Limiter Threshold SZC Disable (Address 19h) .............................................................. 65
6.21 Limiter Release Rate Register (Address 1Ah) ............................................................... 66
6.22 Limiter Attack Rate Register (Address 1Bh) .................................................................. 67
6.23 ALC Enable & Attack Rate (Address 1Ch) .................................................................... 67
6.24 ALC Release Rate (Address 1Dh) ................................................................................. 68
6.25 ALC Threshold (Address 1Eh) ....................................................................................... 69
6.26 Noise Gate Configuration & Misc. (Address 1Fh) .......................................................... 70
6.27 Status (Address 20h) (Read Only) ................................................................................ 71
6.28 Charge Pump Frequency (Address 21h) ....................................................................... 71
7. ANALOG PERFORMANCE PLOTS ...................................................................................... 72
7.1 Headphone THD+N versus Output Power Plots ............................................................. 72
7.2 ADC_FILT+ Capacitor Effects on THD+N ....................................................................... 74
8. EXAMPLE SYSTEM CLOCK FREQUENCIES ...................................................................... 75
8.1 Auto Detect Enabled ........................................................................................................ 75
8.2 Auto Detect Disabled ....................................................................................................... 76
9. PCB LAYOUT CONSIDERATIONS ....................................................................................... 77
9.1 Power Supply, Grounding ................................................................................................ 77
9.2 QFN Thermal Pad ........................................................................................................... 77
4
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