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CS42L56-CNZ PDF预览

CS42L56-CNZ

更新时间: 2024-01-26 04:27:19
品牌 Logo 应用领域
凌云 - CIRRUS 商用集成电路
页数 文件大小 规格书
92页 4002K
描述
Consumer Circuit, 5 X 5 MM, LEAD FREE, MO-220, LQFN-40

CS42L56-CNZ 技术参数

生命周期:Obsolete包装说明:HVQCCN,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:7.85商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-XQCC-N40长度:5 mm
功能数量:1端子数量:40
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度:0.5 mm最大供电电压 (Vsup):2.75 V
最小供电电压 (Vsup):1.62 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.4 mm端子位置:QUAD
宽度:5 mmBase Number Matches:1

CS42L56-CNZ 数据手册

 浏览型号CS42L56-CNZ的Datasheet PDF文件第2页浏览型号CS42L56-CNZ的Datasheet PDF文件第3页浏览型号CS42L56-CNZ的Datasheet PDF文件第4页浏览型号CS42L56-CNZ的Datasheet PDF文件第5页浏览型号CS42L56-CNZ的Datasheet PDF文件第6页浏览型号CS42L56-CNZ的Datasheet PDF文件第7页 
CS42L56  
Ultralow Power, Stereo Codec with Class H Headphone Amp  
DIGITAL to ANALOG FEATURES  
5 mW Stereo Playback Power Consumption  
99 dB Dynamic Range (A-wtd)  
-86 dB THD+N  
ANALOG to DIGITAL FEATURES  
3.5 mW Stereo Record Power Consumption  
95 dB Dynamic Range (A-wtd)  
-87 dB THD+N  
Digital Signal Processing Engine  
Configurable Analog Inputs  
Bass & Treble Tone Control, De-emphasis  
Master Volume Control (+12 to -102 dB in  
0.5 dB steps)  
Soft-ramp & Zero-cross Transitions  
Programmable Peak-detect and Limiter  
Beep Generator with Full Tone Control  
Two Pseudo-differential Stereo Inputs or  
One Pseudo-differential Stereo Inputs +  
One Standard Stereo Input + One Standard  
Mono Input or  
Three Standard Stereo Inputs  
Pseudo-differential Inputs Reduce  
Common Mode Signal Noise  
Stereo Headphone and Line Amplifiers  
3:1 Stereo Input MUX for ADC or  
Passthrough  
Step-down/Inverting Charge Pump  
Analog Programmable Gain Amplifier (PGA)  
Class H Amplifier - Automatic Supply Adj.  
+12 to -6 dB in 0.5 dB steps  
+10 dB or +20 dB Additional Gain for  
Microphone Inputs  
High Efficiency  
Low EMI  
Pseudo-differential Ground-centered Outputs  
High HP Power Output at -75 dB THD+N  
Programmable, Low-noise MIC Bias Output  
Programmable Automatic Level Control (ALC)  
2 x 20 mW Into 16 @ 1.8 V  
Noise Gate for Noise Suppression  
Programmable Threshold &  
Attack/Release Rates  
1 VRMS Line Output @ 1.8 V  
Analog Vol. Ctl. (+12 to -60 dB in 1 dB steps)  
Analog In to Analog Out Passthrough  
Pop and Click Suppression  
Independent ADC Channel Control  
High-pass Filter Disable for DC Measurements  
Analog Supply (VA)  
+1.62 V to +2.75 V  
Charge Pump Supply (VCP)  
Digital Supply (VLDO)  
+1.62 V to +2.75 V  
+1.62 V to +2.75 V  
Step-Down  
Inverting  
+VHP  
-VHP  
LDO Regulator  
ALC  
Beep  
-
Left Headphone Output  
Left Input 1  
Pseudo Diff. Input /  
Left Input 3  
+
Right Input 1  
Pseudo Diff. Input  
Multi-bit  
Mono mix,  
Limiter, Bass,  
Treble Adjust  
Multi-bit  
Attenuator,  
Boost, Mix  
0, +10, or  
+20 dB  
-6 to +12 dB  
0.5 dB Steps  
 DAC  
 ADC  
+
Right Headphone Output  
Left Input 2  
-
Pseudo Diff. Input /  
Right Input 3  
Right Input 2  
ALC  
HPF  
-
Left Line Output  
+
Pseudo Diff. Input  
Control Port  
Serial Audio Port  
Programmable Mic Bias  
Mic Bias Output  
+
-
Right Line Output  
Level Shifter  
Ground-Centered  
Amplifiers  
I²S or Left Justified  
Serial Audio Input/  
Output  
+1.62 V to +3.63 V  
Interface Supply  
I²C or SPI  
Control  
Copyright Cirrus Logic, Inc. 2014  
FEB '14  
DS851F2  
(All Rights Reserved)  
http://www.cirrus.com  

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