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CS42L51 PDF预览

CS42L51

更新时间: 2024-01-24 17:34:00
品牌 Logo 应用领域
凌云 - CIRRUS 解码器编解码器放大器
页数 文件大小 规格书
83页 1355K
描述
Low Power, Stereo CODEC with Headphone Amp

CS42L51 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.04Is Samacsys:N
其他特性:ALSO OPERATE WITH 2.37V TO 2.63V SUPPLY商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8/2.5 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):1.89 V最小供电电压 (Vsup):1.65 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
Base Number Matches:1

CS42L51 数据手册

 浏览型号CS42L51的Datasheet PDF文件第4页浏览型号CS42L51的Datasheet PDF文件第5页浏览型号CS42L51的Datasheet PDF文件第6页浏览型号CS42L51的Datasheet PDF文件第8页浏览型号CS42L51的Datasheet PDF文件第9页浏览型号CS42L51的Datasheet PDF文件第10页 
CS42L51  
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE  
32  
31  
30  
29  
28  
27  
26  
25  
LRCK  
SDA/CDIN (MCLKDIV2)  
SCL/CCLK (I²S/LJ)  
AD0/CS (DEM)  
AIN1B  
AIN1A  
AFILTB  
AFILTA  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
CS42L51  
VA_HP  
AIN2B/BIAS  
AIN2A  
FLYP  
GNDHP  
FLYN  
MICIN2/BIAS/AIN3B  
MICIN1/AIN3A  
9
10  
11  
12  
13  
14  
15  
16  
Pin Name  
#
Pin Description  
LRCK  
1
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the  
serial audio data line.  
SDA/CDIN  
2
3
4
Serial Control Data (Input/Output) - SDA is a data I/O in I²C mode. CDIN is the input data line for the  
control port interface in SPI mode.  
(MCLKDIV2)  
SCL/CCLK  
(I²S/LJ)  
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.  
Serial Control Port Clock (Input) - Serial clock for the serial control port.  
Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-  
mats for the ADC & DAC.  
AD0/CS  
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS  
is the chip select signal for SPI format.  
(DEM)  
VA_HP  
FLYP  
De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.  
5
6
7
8
9
Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.  
Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.  
Analog Ground (Input) - Ground reference for the internal headphone/charge pump section.  
Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.  
GNDHP  
FLYN  
VSS_HP  
Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-  
phone section.  
AOUTB  
AOUTA  
10 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-  
11 tics specification table.  
VA  
12 Analog Power (Input) - Positive power for the internal analog section.  
13 Analog Ground (Input) - Ground reference for the internal analog section.  
AGND  
DS679A2  
7

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