CS 33
Vishay Sfernice
Dual Value Chip Resistors, Center Tap
FEATURES
• Center tap feature
• Small size 30 mil x 30 mil
• Very high ohmic values (up to 5 MΩ)
• Good stability 0.1 % (2000 h, rated power,
at + 70 °C)
Actual Size
• Wirebondable
Chromium silicon thin film is very well suited to produce high
density and high ohmic value resistor chips. Performances
and sizes are greatly improved compared to Thick Film
counterparts. The center tap configuration offers a greater
flexibility for hybrid layout design.
TYPICAL PERFORMANCE
ABS
TRACKING
5 ppm/°C
RATIO
TCR
TOL.
100 ppm/°C
ABS
0.5 %
0.5 %
SCHEMATIC
RT
R1
R2
RT = R1 + R2 with R1 = R2 Standard
STANDARD ELECTRICAL SPECIFICATIONS
TEST
SPECIFICATIONS
PASSIVATED CHROMIUM SILICON
10 kΩ to 5 MΩ
CONDITIONS
MATERIAL
Resistance range
for RT = R1 + R2
- 55 °C to + 155 °C
- 55 °C to + 155 °C
Tracking
Absolute
Ratio
5 ppm/°C
TCR:
100 ppm/°C ( 50 ppm/°C on request)
1/1 standard (unequal values: please consult)
0.5 %, 1 %, 2 %
Ohmic value
Tolerance:
Absolute
Matching
0.5 % standard
Power rating
Stability
250 mW at + 25 °C, 125 mW at + 70 °C, 50 mW at + 125 °C
0.1 % typical, 0.2 maximum
0.1 ppm/V
2000 h at + 70 °C under Pn
Voltage coefficient
Working voltage
100 VDC on RT
Operating temperature range
Storage temperature range
Noise
- 55 °C to + 155 °C
- 55 °C to + 155 °C
< - 20 dB typical
MIL-STD-202 Method 308
1 year at + 25 °C
Thermal EMF
< 0.01 µV/°C
Shelf life stability
200 ppm
* Please see document “Vishay Green and Halogen-Free Definitions (5-2008)” http://www.vishay.com/doc?99902
www.vishay.com
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For technical questions, contact: sfer@vishay.com
Document Number: 60067
Revision: 06-Oct-08