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CS2100P-DZZR PDF预览

CS2100P-DZZR

更新时间： 2024-01-12 18:17:36
品牌 Logo 应用领域
凌云 - CIRRUS 时钟
页数 文件大小 规格书
32页 270K
描述
Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10

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CS2100P-DZZR 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TSSOP, TSSOP10,.19,20Reach Compliance Code：compliant
风险等级：5.7模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：S-PDSO-G10长度：3 mm
功能数量：1端子数量：10
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP10,.19,20封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.1 mm最大供电电流 (Isup)：18 mA
最大供电电压 (Vsup)：3.5 V最小供电电压 (Vsup)：3.1 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：HYBRID温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

CS2100P-DZZR 数据手册

 浏览型号CS2100P-DZZR的Datasheet PDF文件第24页浏览型号CS2100P-DZZR的Datasheet PDF文件第25页浏览型号CS2100P-DZZR的Datasheet PDF文件第26页浏览型号CS2100P-DZZR的Datasheet PDF文件第28页浏览型号CS2100P-DZZR的Datasheet PDF文件第29页浏览型号CS2100P-DZZR的Datasheet PDF文件第30页 
CS2100-CP  
8.3.3  
Enable Device Configuration Registers 1 (EnDevCfg1)  
This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg  
bits can be set in any order and at any time during the control port access sequence, however they must  
both be set before normal operation can occur.  
EnDevCfg1  
Register State  
0
Disabled.  
1
Enabled.  
Application:  
“SPI / I²C Control Port” on page 21  
Note: EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Control Port” on  
page 21.  
8.4  
Global Configuration (Address 05h)  
7
6
5
4
3
2
1
0
Reserved  
Reserved  
Reserved  
Reserved  
Freeze  
Reserved  
Reserved  
EnDevCfg2  
8.4.1  
Device Configuration Freeze (Freeze)  
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)  
but keeps them from taking effect until this bit is cleared.  
FREEZE  
Device Control and Configuration Registers  
0
Register changes take effect immediately.  
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without  
the changes taking effect until after the FREEZE bit is cleared.  
1
8.4.2  
Enable Device Configuration Registers 2 (EnDevCfg2)  
This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg  
bits can be set in any order and at any time during the control port access sequence, however they must  
both be set before normal operation can occur.  
EnDevCfg2  
Register State  
0
Disabled.  
1
Enabled.  
Application:  
“SPI / I²C Control Port” on page 21  
Note: EnDevCfg1 must also be set to enable control port mode. See “SPI / I²C Control Port” on  
page 21.  
8.5  
Ratio (Address 06h - 09h)  
7
6
5
4
3
2
1
0
MSB  
MSB-8  
LSB+15  
LSB+7  
...................................................................................................................................................  
...................................................................................................................................................  
...................................................................................................................................................  
...................................................................................................................................................  
MSB-7  
MSB-15  
LSB+8  
LSB  
These registers contain the User Defined Ratio as shown in the “Register Quick Reference” section on  
page 24. These 4 registers form a single 32-bit ratio value as shown above. See “Output to Input Frequency  
Ratio Configuration” on page 17 and “Calculating the User Defined Ratio” on page 30 for more details.  
DS840F1  
27  
1...24252627282930...32

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