Part Number - S1201QFI22
Product Brief Revision 3.4 - February 2002
Datasheet Revision 3.1
PRODUCT BRIEF
CONGO
STS-12c/STS-3c POS/ATM SONET MAPPER
Features
General Description
• Processes SONET/SDH STS-12c/(STM-4/AU-4-4c) or
STS-3c/STM-1 data streams with full duplex mapping of
ATM cells or packets (PPP or LAPS) into SONET/SDH
payloads.
The S1201 is a highly-integrated VLSI device that provides
full-duplex mapping of PPP/LAPS encapsulated packets or
ATM cells into STS-12c/AU-4-4c or STS-3c/AU-4 payloads.
The S1201 supports full-duplex processing of SONET/SDH
data streams with full section, line, and path overhead pro-
cessing. The device supports framing pattern, scram-
bling/descrambling, alarm signal insertion/detection, and bit
interleaved parity (B1/B2/B3) processing. Serial interfaces for
SONET/SDH TOH overhead bytes are also provided.
• Terminates & generates SONET/SDH section, line, & path
layers, with transport/section E1, E2, F1 and DCC over-
head interfaces in both transmit and receive directions.
• Provides an 8-bit parallel line-side interface operating at
19.44/77.76 MHz, and a 16-bit Utopia Level 2 or
POS-PHYTM Level 2 compatible system-side interface at
25/50 MHz.
The S1201 provides a line-side interface that can operate at
622.08 Mb/s (8-bit bus at 77.76 MHz) or 155.52 Mb/s (8-bit
bus at 19.44 MHz). For ATM applications, a UTOPIA Level 2
system interface, operating at either 25 or 50 MHz is pro-
vided. For Packet-over-SONET applications, a POS-PHYTM
Level 2 compatible interface is provided.
• Generic 8-bit microprocessor interface for configuration,
control, and status monitoring.
• Scrambling/descrambling (1+X6+X7) of SONET/SDH
frame.
The S1201 is standards compliant with Bellcore GR-253, ITU
G.707, ANSI T1.105 -1995, IETF RFCs 1619/1661/1662/
2615 (PPP) and ITU-T COM 7-224-E/D307 (LAPS recom-
mendation) protocols.
• Selectable self-synchronous scrambler implementing (X43
+1) polynomial for ATM and HDLC.
• Supports multiple devices sharing the same Utopia inter-
face when used in a multi-PHY configuration.
ATM support includes insertion and extraction of ATM cells
into and out of the SONET/SDH SPE, scrambling/descram-
bling, header error control (HEC) detection and correction,
idle cell generation and filtering, and generation of perfor-
mance monitoring counts for TX, RX, ERR, dropped and idle
cells.
• Provides an 8-bit General Purpose I/O (GPIO) register and
associated hardware interface pins.
• Provides an IEEE 1149.1 JTAG (Boundary Scan) test port.
• Provides internal loopback paths for diagnostics.
• Implemented in 0.35um/3.3V CMOS process technology
• Packaged in 208 pin PQFP.
HDLC support includes framing, transparency processing,
optional 16/32 FCS processing, and self synchronous scram-
bling/descrambling (X43+1). It also supports a direct
flow-thru mode where the system data is passed directly to or
from the SPE.
S1201 Block Diagram
TX_ERR
TX_EOP
TX_MOD
TX_SYS_DAT[15:0]
TX
CELL/PKT
FIFO
TX_ADR[4:0]
TX_CLK
TOH INSERT
MICROPROCESSOR I/F
TX
TX_DATA[7:0]
TX_PRTY
TX_SONET_CLK
TX_FRAME_OUT
FRAMER
TX ATM/HDLC
(PPP/LAPS)
PROC
TX_ENB
SPE/VC & POH
GENERATE
TX_SOC(P)
TX_CLAV(PTPA)
TX_STPA
SCRAMBLE
POH
RX ATM/HDLC
(PPP/LAPS)
PROC
RX_SYS_DAT[15:0]
TOH
MONITOR
RX
DE-SCRAMBLE
RX_DATA[7:0]
RX_SONET_CLK
RX_FRAME_IN
RX_LOS
MONITOR
RX_ADR[4:0]
RX_CLK
FRAMER
RX ATM/HDLC
(PPP/LAPS)
CNTRS
POINTER
INTERPRET
RX_PRTY
RX_ENB
RX
CELL/PKT
FIFO
TOH EXTRACT
RX_SOC(P)
RX_CLAV(PRPA)
RX_RVAL
JTAG PORT
GPIO REG
RX_MOD
RX_EOP
RX_ERR
Production Information - The information contained in this
document is about a product in its fully tested and character-
ized phase. All features described herein are supported. Con-
tact AMCC for updates to this document and the latest product
status.
AMCC
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