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CS1087XFNR44 PDF预览

CS1087XFNR44

更新时间: 2024-01-19 04:39:53
品牌 Logo 应用领域
安森美 - ONSEMI 显示驱动器驱动程序和接口接口集成电路
页数 文件大小 规格书
12页 119K
描述
Vacuum Fluorescent Display Tube Driver

CS1087XFNR44 技术参数

生命周期:Obsolete包装说明:PLASTIC, LCC-44
Reach Compliance Code:unknown风险等级:5.84
数据输入模式:SERIAL显示模式:DOT MATRIX
接口集成电路类型:VACUUM FLUORESCENT DISPLAY DRIVERJESD-30 代码:S-PQCC-J44
复用显示功能:YES功能数量:1
区段数:32端子数量:44
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
最大供电电压:16.5 V最小供电电压:8 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:J BEND端子位置:QUAD
最小 fmax:2 MHzBase Number Matches:1

CS1087XFNR44 数据手册

 浏览型号CS1087XFNR44的Datasheet PDF文件第2页浏览型号CS1087XFNR44的Datasheet PDF文件第3页浏览型号CS1087XFNR44的Datasheet PDF文件第4页浏览型号CS1087XFNR44的Datasheet PDF文件第6页浏览型号CS1087XFNR44的Datasheet PDF文件第7页浏览型号CS1087XFNR44的Datasheet PDF文件第8页 
CS1087  
GRID1 GRID2 GRID3  
AN1  
AN2  
AN3  
AN23 AN24 AN25 AN26 AN27 AN28 AN29  
V
BB  
V
REG  
POR  
V
REG  
GND  
V
REG  
GREN  
STB  
METAL MASK ROM  
V
V
V
REG  
REG  
REG  
D
Q
Q
D
Q
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
Q
D
Q
D
Q
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
LE  
D
V
REG  
IN  
D
OUT  
D
CLK  
Q
D
CLK  
D
CLK  
Q
D
CLK  
D
CLK  
D
CLK  
D
Q
D
Q
D
Q
CLK  
D
Q
D
Q
D
D
Q
D Q  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
R
R
R
R
R
R
R
R
R
R
R
R
R
R
CLK  
Output Drive Capability  
Grid Outputs: 50 mA  
AN24–AN29: 20 mA  
AN1–AN23: 2.0 mA  
Figure 2. Block Diagram  
OPERATION DESCRIPTION  
Upon the initial application of power, the power on reset  
The three GRID outputs are gated by the GREN input.  
When GREN is low, the GRID outputs are forced low  
regardless of the state of the corresponding latch output.  
When GREN is high, the GRID outputs correspond to the  
state of their respective latch outputs. The anode outputs,  
AN1 to AN29 are always enabled.  
function will cause all of the anode and grid driver outputs  
to be off and all shift register outputs to be set low. Data is  
fed into the shift register through the D pin at the rising  
IN  
edge of the CLK input. Thirty two bits of data are capable of  
being stored by the shift register. Once the desired pattern is  
stored in the shift register, it can be transferred to the latch  
by setting the STB input high. The output of each latch  
drives its corresponding output stage. A logic high input to  
the shift register/latch will cause the corresponding output  
to turn on. A logic low input to the shift register/latch will  
cause the corresponding output to turn off. Please note that  
if the STB is held high, the outputs of the latch reflect the  
outputs of the corresponding shift register bits and will  
change if data is shifted in.  
The D  
pin is the output of the last stage of the shift  
OUT  
register to allow serial cascading of this IC with other  
devices. Data from the last stage of the shift register is  
supplied to the D  
pin delayed by 1/2 CLK cycle. Data on  
OUT  
the D  
output changes with the falling edges of the CLK  
OUT  
to prevent logic race conditions between the CLK and the  
of the next IC in the serial chain.  
D
IN  
http://onsemi.com  
5

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