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CP82C89

更新时间： 2024-02-10 20:06:42
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路光电二极管时钟
页数 文件大小 规格书
15页 126K
描述
CMOS Bus Arbiter

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中文翻译

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CP82C89 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：compliant风险等级：5.11
Is Samacsys：N总线兼容性：8089; 80C88; 8088; 80C86; 8086
最大时钟频率：8 MHzJESD-30 代码：R-PDIP-T20
JESD-609代码：e3长度：25.895 mm
端子数量：20最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT APPLICABLE电源：5 V
认证状态：Not Qualified座面最大高度：5.33 mm
子类别：System Interface Logic ICs最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT APPLICABLE
宽度：7.62 mmuPs/uCs/外围集成电路类型：SYSTEM INTERFACE LOGIC, BUS ARBITER AND CONTINUOUS SIGNAL GENERATOR
Base Number Matches：1

CP82C89 数据手册

 浏览型号CP82C89的Datasheet PDF文件第1页浏览型号CP82C89的Datasheet PDF文件第3页浏览型号CP82C89的Datasheet PDF文件第4页浏览型号CP82C89的Datasheet PDF文件第5页浏览型号CP82C89的Datasheet PDF文件第6页浏览型号CP82C89的Datasheet PDF文件第7页 
82C89  
Functional Diagram  
INIT  
ARBITRATION  
BCLK  
BREQ  
BPRN  
BPRO  
TM  
MULTIBUS  
MULTIBUS  
INTERFACE  
COMMAND  
SIGNALS  
S
S
S
2
1
0
80C86/  
80C88  
STATUS  
STATUS  
BUSY  
CBRQ  
DECODER  
LOCK  
CLK  
CONTROL/  
STRAPPING  
OPTIONS  
CRQLCK  
RESB  
ANYRQST  
CONTROL  
LOCAL  
BUS  
AEN  
INTERFACE  
SYSTEM  
SIGNALS  
IOB  
SYSB/  
RESB  
+5V  
GND  
TM  
MULTIBUS  
IS AN INTEL CORP. TRADEMARK  
Pin Description  
PIN  
SYMBOL  
NUMBER  
TYPE  
DESCRIPTION  
V
20  
V
: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for  
CC  
CC  
decoupling.  
GND  
10  
GROUND.  
S0, S1, S2  
1, 18-19  
I
I
I
I
I
STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The  
82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1).  
CLK  
LOCK  
17  
16  
15  
4
CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions  
are initiated.  
LOCK: A processor generated signal which when activated (low) prevents the arbiter from surren-  
dering the multi-master system bus to any other bus arbiter, regardless of its priority.  
CRQLCK  
RESB  
COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the  
multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin.  
RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a  
multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is re-  
quested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB  
input is ignored.  
ANYRQST  
14  
I
ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered  
to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter  
requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible).  
When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Informa-  
tion. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of  
the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to sur-  
render the multi-master system bus after each transfer cycle. Note that when surrender occurs  
BREQ is driven false (high).  
4-344  
1234567...15

中文翻译

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CP82C89 替代型号

型号 品牌 替代类型 描述 数据表
CP82C89Z INTERSIL

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