Datasheet > CP82C89

CP82C89

更新时间： 2024-01-09 20:02:00

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路光电二极管时钟
页数	文件大小	规格书
15页	126K
描述
CMOS Bus Arbiter

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技术参数
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CP82C89 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP20,.3	针数：	20
Reach Compliance Code：	compliant	风险等级：	5.11
Is Samacsys：	N	总线兼容性：	8089; 80C88; 8088; 80C86; 8086
最大时钟频率：	8 MHz	JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e3	长度：	25.895 mm
端子数量：	20	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP20,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	5.33 mm
子类别：	System Interface Logic ICs	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	7.62 mm	uPs/uCs/外围集成电路类型：	SYSTEM INTERFACE LOGIC, BUS ARBITER AND CONTINUOUS SIGNAL GENERATOR
Base Number Matches：	1

CP82C89 数据手册

82C89

Serial Priority Resolving

techniques. It allows for many arbiters to be present on the

bus while not requiring too much logic to implement.

The serial priority resolving technique eliminates the need

for the priority encoder-decoder arrangement by daisychain- 82C89 Modes Of Operation

ing the bus arbiters together, connecting the higher priority

bus arbiter’s BPRO (Bus Priority Out) output to the BPRN of

the next lower priority. See Figure 3.

There are two types of processors for which the 82C89 will

provide support: An Input/Output processor (i.e. an NMOS

8089 IOP) and the 80C86, 80C88. Consequently, there are

two basic operating modes in the 82C89 bus arbiter. One,

the IOB (I/O Peripheral Bus) mode, permits the processor

access to both an I/O Peripheral Bus and a multi-master sys-

tem bus. The second, the RESB (Resident Bus mode), per-

mits the processor to communicate over both a Resident

Bus and a multi-master system bus. An I/O Peripheral Bus is

a bus where all devices on that bus, including memory, are

treated as I/O devices and are addressed by I/O commands.

All memory commands are directed to another bus, the

multi-master system bus. A Resident Bus can issue both

memory and I/O commands, but it is a distinct and separate

bus from the multi-master system bus. The distinction is that

the Resident Bus has only one master, providing full avail-

ability and being dedicated to that one master.

BPRN

BUS

ARBITER

BPRO

BPRN

BUS

ARBITER

BPRO

BPRN

BUS

ARBITER

BPRO

BPRN

BUS

ARBITER

BPRO

The IOB strapping option conﬁgures the 82C89 Bus Arbiter

into the IOB mode and the strapping option RESB conﬁg-

ures it into the RESB mode. It might be noted at this point

that if both strapping options are strapped false, the arbiter

interfaces the processor to a multi-master system bus only

(see Figure 4). With both options strapped true, the arbiter

interfaces the processor to a multi-master system bus, a

Resident Bus, and an I/O Bus.

•

CBRQ BUSY

FIGURE 3. SERIAL PRIORITY RESOLVING

NOTE: The number of arbiters that may be daisy-chained together

in the serial priority resolving scheme is a function of BCLK and the

propagation delay from arbiter to arbiter. Normally, at 10MHz only 3

arbiters may be daisychained.

In the IOB mode, the processor communicates and controls

a host of peripherals over the Peripheral Bus. When the I/O

Processor needs to communicate with system memory, it

does so over the system memory bus. Figure 5 shows a pos-

sible I/O Processor system conﬁguration.

Rotating Priority Resolving

The rotating priority resolving technique is similar to that of

the parallel priority resolving technique except that priority is

dynamically re-assigned. The priority encoder is replaced by

a more complex circuit which rotates priority between

requesting arbiters thus allowing each arbiter an equal

chance to use the multi-master system bus, over time.

The 80C86 and 80C88 processors can communicate with a

Resident Bus and a multi-master system bus. Two bus con-

trollers and only one Bus Arbiter would be needed in such a

conﬁguration as shown in Figure 6. In such a system conﬁg-

uration the processor would have access to memory and

peripherals of both busses. Memory mapping techniques are

applied to select which bus is to be accessed. The

SYSB/RESB input on the arbiter serves to instruct the arbi-

ter as to whether or not the system bus is to be accessed.

The signal connected to SYSB/RESB also enables or dis-

ables commands from one of the bus controllers. A sum-

mary of the modes that the 82C89 has, along with its

response to its status lines inputs, is shown in Table 1.

Which Priority Resolving Technique To Use

There are advantages and disadvantages for each of the

techniques described above. The rotating priority resolving

technique requires substantial external logic to implement

while the serial technique uses no external logic but can

accommodate only a limited number of bus arbiters before the

daisy-chain propagation delay exceeds the multimaster’s sys-

tem bus clock (BCLK). The parallel priority resolving tech-

nique is in general a good compromise between the other two

4-347

1 2 3 456 7 8...15

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CP82C89 替代型号

型号	品牌	替代类型	描述	数据表
CP82C89Z	INTERSIL	类似代替	CMOS Bus Arbiter
CP82C88	INTERSIL	类似代替	CMOS Bus Controller
CP82C88Z	INTERSIL	功能相似	CMOS Bus Controller

与CP82C89相关器件

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CP835N3D	JSMC	获取价格	TO-220MF-K1
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CP85H	CUI	获取价格	PELTIER MODULE
CP85H_17	CUI	获取价格	PELTIER MODULE

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