Datasheet > CP82C88Z

CP82C88Z

更新时间： 2024-02-14 05:25:32

品牌	Logo	应用领域
英特矽尔 - INTERSIL		总线控制器
页数	文件大小	规格书
11页	252K
描述
CMOS Bus Controller

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CP82C88Z 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP20,.3	针数：	20
Reach Compliance Code：	compliant	风险等级：	5.05
总线兼容性：	80188; 80186; 8089; 80C88; 8088; 80C86; 8086	最大时钟频率：	8 MHz
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e3
长度：	25.895 mm	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT APPLICABLE
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	5.33 mm	子类别：	Bus Controllers
最大压摆率：	1 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	7.62 mm	uPs/uCs/外围集成电路类型：	SYSTEM INTERFACE LOGIC, CONTROL AND COMMAND SIGNAL GENERATOR
Base Number Matches：	1

CP82C88Z 数据手册

82C88

Control Outputs

Address Latch Enable and Halt

The control outputs of the 82C88 are Data Enable (DEN),

Data Transmit/Receive (DT/R) and Master Cascade Enable/

Peripheral Data Enable (MCE/PDEN). The DEN signal

determines when the external bus should be enabled onto

the local bus and the DT/R determines the direction of data

transfer. These two signals usually go to the chip select and

direction pins of a transceiver.

Address Latch Enable (ALE) occurs during each machine

cycle and serves to strobe the current address into the

82C82/82C83H address latches. ALE also serves to strobe

the status (S0, S1, S2) into a latch for halt state decoding.

Command Enable

The Command Enable (CEN) input acts as a command

qualifier for the 82C88. If the CEN pin is high, the 82C88

functions normally. If the CEN pin is pulled LOW, all

command lines are held in their inactive state (not three-

state). This feature can be used to implement memory

partitioning and to eliminate address conflicts between

system bus devices and resident bus devices.

The MCE/PDEN pin changes function with the two modes of

the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),

the PDEN signal serves as a dedicated data enable signal

for the I/O or Peripheral System bus.

Interrupt Acknowledge and MCE

The MCE signal is used during an interrupt acknowledge

cycle if the 82C88 is in the System Bus mode (IOB LOW).

During any interrupt sequence, there are two interrupt

acknowledge cycles that occur back to back. During the first

interrupt cycle no data or address transfers take place. Logic

should be provided to mask off MCE during this cycle. Just

before the second cycle begins the MCE signal gates a

master Priority Interrupt Controller’s (PIC) cascade address

onto the processor’s local bus where ALE (Address Latch

Enable) strobes it into the address latches. On the leading

edge of the second interrupt cycle, the addressed slave PIC

gates an interrupt vector onto the system data bus where it is

read by the processor.

If the system contains only one PIC, the MCE signal is not

used. In this case, the second Interrupt Acknowledge signal

gates the interrupt vector onto the processor bus.

FN2979.2

August 25, 2005

1 2 345 6 7...11

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