Datasheet > CP82C88Z

CP82C88Z

更新时间： 2024-02-15 19:08:13

品牌	Logo	应用领域
英特矽尔 - INTERSIL		总线控制器
页数	文件大小	规格书
11页	252K
描述
CMOS Bus Controller

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CP82C88Z 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP20,.3	针数：	20
Reach Compliance Code：	compliant	风险等级：	5.05
总线兼容性：	80188; 80186; 8089; 80C88; 8088; 80C86; 8086	最大时钟频率：	8 MHz
JESD-30 代码：	R-PDIP-T20	JESD-609代码：	e3
长度：	25.895 mm	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT APPLICABLE
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	5.33 mm	子类别：	Bus Controllers
最大压摆率：	1 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	7.62 mm	uPs/uCs/外围集成电路类型：	SYSTEM INTERFACE LOGIC, CONTROL AND COMMAND SIGNAL GENERATOR
Base Number Matches：	1

CP82C88Z 数据手册

82C88

Pin Des cription (Continued)

SYMBOL NUMBER TYPE

DESCRIPTION

AMWC

ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the machine

cycle to give memory devices an early indication of a write instruction. Its timing is the same as a read command

signal. AMWC is active LOW.

MWTC

MRDC

MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on the data

bus. This signal is active LOW.

MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data bus. MRDC

is active LOW.

INTA

INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its interrupt has been

acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW.

MCE/PDEN

This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable occurs during an interrupt sequence

and serves to read a Cascade Address from a master 82C59A Priority Interrupt Controller onto the data bus. The

MCE signal is active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables the data bus transceiver

for the I/O bus that DEN performs for the system bus. PDEN is active LOW.

Functional Des cription

The command logic decodes the three 80C86, 8086, 80C88,

8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to

determine what command is to be issued (see Table 1).

IOB mode if I/O or peripherals dedicated to one processor

exist in a multi-processor system.

System Bus Mode

TABLE 1. COMMAND DECODE DEFINITION

The 82C88 is in the System Bus mode if the IOB pin is

strapped LOW. In this mode, no command is issued until a

specified time period after the AEN line is activated (LOW).

This mode assumes bus arbitration logic will inform the bus

controller (on the AEN line) when the bus is free for use.

Both memory and I/O commands wait for bus arbitration.

This mode is used when only one bus exists. Here, both I/O

and memory are shared by more than one processor.

82C88

PROCESSOR STATE

COMMAND

Interrupt Acknowledge INTA

Read I/O Port

Write I/O Port

Halt

IORC

IOWC, AIOWC

None

Command Outputs

Code Access

Read Memory

Write Memory

Passive

MRDC

The advanced write commands are made available to initiate

write procedures early in the machine cycle. This signal can

be used to prevent the processor from entering an

unnecessary wait state.

MRDC

MWTC, AMWC

None

INTA (Interrupt Acknowledge) acts as an I/O read during an

interrupt cycle. Its purpose is to inform an interrupting device

that its interrupt is being acknowledged and that it should

place vectoring information onto the data bus.

I/O Bus Mode

The 82C88 is in the I/O Bus mode if the IOB pin is strapped

HIGH. In the I/O Bus mode, all I/O command lines IORC,

IOWC, AIOWC, INTA) are always enabled (i.e., not

dependent on AEN). When an I/O command is initiated by

the processor, the 82C88 immediately activates the

command lines using PDEN and DT/R to control the I/O bus

transceiver. The I/O command lines should not be used to

control the system bus in this configuration because no

arbitration is present. This mode allows one 82C88 Bus

Controller to handle two external busses. No waiting is

involved when the CPU wants to gain access to the I/O bus.

Normal memory access requires a “Bus Ready” signal (AEN

LOW) before it will proceed. It is advantageous to use the

The command outputs are:

MRDC - Memory Read Command

MWTC - Memory Write Command

IORC - I/O Read Command

IOWC - I/O Write Command

AMWC - Advanced Memory Write Command

AIOWC - Advanced I/O Write Command

INTA - Interrupt Acknowledge

FN2979.2

August 25, 2005

1 234 5 6 7...11

下载PDF

与CP82C88Z相关器件

型号	品牌	描述	获取价格	数据表
CP82C89	INTERSIL	CMOS Bus Arbiter	获取价格
CP82C89Z	INTERSIL	CMOS Bus Arbiter	获取价格
CP835N3C	JSMC	TO-220C	获取价格
CP835N3D	JSMC	TO-220MF-K1	获取价格
CP850N3C	JSMC	TO-220MF-K1	获取价格
CP85138	CUI	PELTIER MODU LE	获取价格

与CP82C88Z相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

18
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

18
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

14
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

11

产品中心

服务支持

精选活动

关于我们

帮助中心

CP82C88Z

CP82C88Z 技术参数

CP82C88Z 数据手册

与CP82C88Z相关器件

与CP82C88Z相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CP82C88Z

CP82C88Z 技术参数

CP82C88Z 数据手册

与CP82C88Z相关器件

与CP82C88Z相关文章

您还可以找

您在本页遇到什么问题？