Datasheet > CP82C86H-5

CP82C86H-5

更新时间： 2024-01-09 21:57:05

品牌	Logo	应用领域
英特矽尔 - INTERSIL		总线收发器
页数	文件大小	规格书
8页	112K
描述
CMOS Octal Bus Transceiver

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技术参数
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CP82C86H-5 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	unknown
风险等级：	5.8	其他特性：	GATED INPUTS ELIMINATE THE NEED FOR PULL-UP RESISTORS
控制类型：	COMMON CONTROL	计数方向：	BIDIRECTIONAL
系列：	CMOS	JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e0	负载电容（CL）：	300 pF
逻辑集成电路类型：	BUS TRANSCEIVER	最大I（ol）：	0.02 A
位数：	8	功能数量：	1
端口数量：	2	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
Prop。Delay @ Nom-Sup：	65 ns	传播延迟（tpd）：	35 ns
认证状态：	Not Qualified	子类别：	Bus Driver/Transceivers
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
翻译：	N/A	Base Number Matches：	1

CP82C86H-5 数据手册

82C86H

Decoupling Capacitors

Functional Diagram

The transient current required to charge and discharge the

300pF load capacitance speciﬁed in the 82C86H/87H data

sheet is determined by:

(EQ. 1)

I = C (dv ⁄ dt)

Assuming that all outputs change state at the same time and

that dv/dt is constant;

(EQ. 2)

(V CC × 80%)

------------------------------------

tR ⁄ tF

I = C

where tR = 20ns, V_CC= 5.0V, C_L= 300pF on each eight out-

puts.

–12

–9

I = (80 × 300 × 10

= 480mA

) × (5.0V × 0.8) ⁄ (20 × 10

)

(EQ. 3)

V_CC

Gated Inputs

During normal system operation of a latch, signals on the

bus at the device inputs will become high impedance or

make transitions unrelated to the operation of the latch.

These unrelated input transitions switch the input circuitry

and typically cause an increase in power dissipation in

CMOS devices by creating a low resistance path between

STB

INTERNAL

DATA

DATA IN

_CCand GND when the signal is at or near the input switch-

ing threshold. Additionally, if the driving signal becomes high

impedance (“ﬂoat” condition), it could create an indetermi-

nate logic state at the inputs and cause a disruption in

device operation.

FIGURE 1. 82C82/83H

V_CC

The Intersil 82C8X series of bus drivers eliminates these

conditions by turning off data inputs when data is latched

(STB = logic zero for the 82C82/83H) and when the device is

disabled (OE = logic one for the 82C86H/87H). These gated

inputs disconnect the input circuitry from the V_CCand

ground power supply pins by turning off the upper P-channel

and lower N-channel (See Figures 1 and 2). No current ﬂow

from V_CCto GND occurs during input transitions and invalid

logic states from ﬂoating inputs are not transmitted. The next

stage is held to a valid logic level internal to the device.

INTERNAL

DATA

DATA IN

V_CC

D.C. input voltage levels can also cause an increase in ICC if

these input levels approach the minimum V_IHor maximum

V_ILconditions. This is due to the operation of the input cir-

cuitry in its linear operating region (partially conducting

state). The 82C8X series gated inputs mean that this condi-

tion will occur only during the time the device is in the trans-

parent mode (STB = logic one). ICC remains below the

maximum ICC standby speciﬁcation of 10µA during the time

inputs are disabled, thereby greatly reducing the average

power dissipation of the 82C8X series devices.

FIGURE 2. 82C86H/87H GATED INPUTS

This current spike may cause a large negative voltage spike

on V_CCwhich could cause improper operation of the device.

To ﬁlter out this noise, it is recommended that a 0.1µF

ceramic disc capacitor be placed between V_CCand GND at

each device, with placement being as near to the device as

possible.

4-319

1 234 5 6 7 8

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