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CP82C84AZ PDF预览

CP82C84AZ

更新时间： 2024-01-20 01:29:02
品牌 Logo 应用领域
英特矽尔 - INTERSIL 驱动器时钟发生器
页数 文件大小 规格书
11页 291K
描述
CMOS Clock Generator Driver

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CP82C84AZ 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：DIP, DIP18,.3Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.75JESD-30 代码：R-PDIP-T18
JESD-609代码：e0端子数量：18
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：24 MHz封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP18,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V主时钟/晶体标称频率：24 MHz
认证状态：Not Qualified子类别：Clock Generators
最大压摆率：40 mA最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

CP82C84AZ 数据手册

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82C84A  
Pin Des cription  
SYMBOL  
NUMBER  
TYPE  
DESCRIPTION  
AEN1,  
AEN2  
3, 7  
I
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready  
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are  
useful in system configurations which permit the processor to access two Multi-Master System Busses.  
In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW).  
RDY1,  
RDY2  
4, 6  
15  
I
I
BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device  
located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1  
while RDY2 is qualified by AEN2.  
ASYNC  
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of  
the READY logic. When ASYNC is low, two stages of READY synchronization are provided. When  
ASYNC is left open or HIGH, a single stage of READY synchronization is provided.  
READY  
X1, X2  
F/C  
5
O
I O  
I
READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is  
cleared after the guaranteed hold time to the processor has been met.  
17, 16  
13  
CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times  
the desired processor clock frequency, (Note 1).  
FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits the  
processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is generated for the  
EFI input, (Note 1).  
EFI  
14  
8
I
EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input frequency  
appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK  
output.  
CLK  
O
PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which directly  
connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crystal or EFI  
input frequency and a 1/3 duty cycle.  
PCLK  
OSC  
RES  
2
O
O
I
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK  
and has a 50% duty cycle.  
12  
11  
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to  
that of the crystal.  
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A provides a  
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper  
duration.  
RESET  
CSYNC  
10  
1
O
I
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing  
characteristics are determined by RES.  
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be  
synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset.  
When CSYNC goes LOW the internal counters are allowed to resume counting. CSYNC needs to be  
externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to  
ground.  
GND  
9
Ground  
V
18  
V
: The +5V power supply pin. A 0.1µF capacitor between V  
and GND is recommended for  
CC  
CC  
CC  
decoupling.  
NOTE:  
1. If the crystal inputs are not used X1 must be tied to V  
or GND and X2 should be left open.  
CC  
FN2974.3  
December 6, 2005  
3
1234567...11

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