Datasheet > CEU71A3

CEU71A3

更新时间： 2022-10-21 09:44:38

品牌	Logo	应用领域
华瑞 - CET		晶体晶体管场效应晶体管
页数	文件大小	规格书
5页	58K
描述
N-Channel Logic Level Enhancement Mode Field Effect Transistor

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数据手册

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CEU71A3 数据手册

CED71A3/CEU71A3

1.15

1.30

ID=250ĳA

DS=VGS

1.10

1.20

=250ĳA

1.10

1.00

0.90

1.05

1.00

0.95

0.90

0.85

0.80

0.70

0.60

-50 -25

25 50 75 100 125 150

-50 -25

25 50

75 100 125 150

Tj, Junction Temperature ( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 6. Breakdown Voltage Variation

with Temperature

1.0

0.1

DS=5V

1.2

0.4

0.6

0.8

1.0

1.4

IDS, Drain-Source Current (A)

VSD, Body Diode Forward Voltage (V)

Figure 7. Transconductance Variation

with Drain Current

Figure 8. Body Diode Forward Voltage

Variation with Source Current

DS=15V

D=15A

Limit

RDS(O

-1

įJA=

=25 C

40 C/W

Single Pulse

-2

-1

-2

Qg, Total Gate Charge (nC)

VDS, Drain-Source Voltage (V)

Figure 10. Maximum Safe

Operating Area

Figure 9. Gate Charge

6-70

1 2 345

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