CE61 Series (0.28µm Leff) Embedded Array
Mixed-Signal Macros
D/A Converters
High-Performance Functions
• MPEG2 (Q1 ’99)
• 8-bit, 30 MHz (video)
• 8-bit, 50 MHz (video)
• 8-bit, 220 MHz (video)
• 10-bit, 1.5 MHz (general purpose)
• 8-bit, 200 kHz (general purpose)
• 16/64/256 QAM (Q1 ’99)
• QPSK (Q1 ’99)
ASIC Design Kit and EDA Support
Verifire
VCS, Verilog-XL,
(VCS, Cadence Tools,
Synopsys, Synthesis)
Sign-off Simulation, Veritime,
Verifault, Design Compiler (Synopsys)
A/D Converters
• 8-bit, 50 MHz (video)
• 6-bit, 300 MHz (disk drive)
• 10-bit, 20 MHz (digital communications)
• 8-bit, 400 kHz (general purpose)
• 10-bit, 1 MHz (general purpose)
Vhdlfire
All Vital compliance tools,
Sign-off Simulation, Design Time,
Design Compiler
Other EDA Tools
Motive, Sunrise, HLD, DesignPower
Multiplier Compiler
• Multiplicand (m): 4 ≤ m ≤ 32
• Multiplier (n): 4 ≤ n ≤ 32 (even numbers only)
PACKAGE AVAILABILITY
Frame Size
No. of Pins
QFP Package (1.0, 0.8, 0.65 mm pitch)
Memory Macros
• SRAM Compiler: single and dual port (1 R/W, 1R), up to
72K bits per block
64
80
100
120
160
F10
F10
F10
F10, E7/8/9/15/19/25/35/45
E7/8/9/15/19/25/35/45/59, F20/30/40/50/60/70/80
• ROM Compiler: up to 512K bits per block
Phase Locked Loops
Shrink QFP Package (0.5 mm pitch)
• Digital: 180 to 360 MHz
• Analog: 50 to 200 MHz
64
80
100
120
E7/8/9, F10
E7/8/9, F10
E9/15, F10
I/Os
E7/8/9/15/19/25/35/45, F10
E7/8/9/15/19/25/35/45, F20/30/40/50
E8/9/15/19/25/35/45, F20/30/40/50
E9/15/19/25/35/45/59, F20/30/40/50/60/70/80
E15/19/25/35/45/59, F30/40/50/60/70
F40/50/60/70/80
• 5V, 3.3V and 5V tolerant
• Slew-rate controlled
• CMOS, TTL, PCML/PECL, LVDS, PCI, SSTL, 1284,
GTL+
144
176
208
240
256
IPs and Mega Macros
304
F50/60/70/80
To achieve the highest level of integration for our cus-
tomers, Fujitsu offers a rich set of intellectual properties
(IPs), developed either internally or acquired through
strategic relationships with IP providers.
Interface Functions
256 (0.4 mm)
E19/25/35/45/59
Heatspreader QFP Package (0.5 mm pitch)
208
240
256
304
256 (0.4 mm)
E9/15/19/25/35/45/59/71, F20/30/40/50/60/70/80
E15/19/25/35/45/58/71, F30/40/50/60/70/80
F40/50/60/70/80
E35/45/59/71, F50/60/70/80
E19/25/35/45/59/71
• ARC: 32-bit embedded core
®
• OakDSPCore : 16-bit fixed point DSP core
Ball Grid Array (1.27 mm pitch)
• PCI core
• 10/100 Ethernet MAC
• P1394
256
352
420
576
672
E15/19, F40/50
E25/35, F60/70
E35/45, F60/70
E45/59
• USB
E71
FUJITSU MICROELECTRONICS, INC.
Corporate Headquarters
© 1998 Fujitsu Microelectronics, Inc.
3545 North First Street, San Jose, California 95134-1804
Tel: (800) 866-8608 Fax: (408) 922-9179
E-mail: fmicrc@fmi.fujitsu.com Internet: http://www.fujitsumicro.com
All company and product names are trademarks or
registered trademarks of their respective owners.
Printed in the U.S.A. ASIC-FS-20505-7/98
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