CE61 Series Embedded Array
0.28µm Leff
Features
• 0.28µm L (0.35µm drawn)
eff
5V I/O
5V I/O
5V I/O
5V I/O
5V I/O
3V I/O
3V I/O
3V I/O
PCML
3V I/O
3V I/O
5V I/O
5V I/O
5V I/O
5V I/O
5V I/O
• Propagation delay of 85 ps
Fixed
Layout
• Mixed-signal macros–A/D and D/A converters
• High density diffused RAMs and ROMs
• Separate core and I/O supply voltages
• I/Os–5V, 3.3V and 5V tolerant
• 70µm staggered pad pitch for pad-limited designs
• High performance and special I/Os–311 PCML,
250 MHz LVDS, PCI, SSTL
Soft Macro
Embedded
Hard
Macro
Clk
Clock Tree
Fixed
Layout
Soft Macro
• Analog and digital PLLs
• Packaging options–QFP, HQFP, BGA
• Support for major third-party EDA tools
Description
E-series, 70µm Staggered Pad Pitch
Optimized for Pad-Limited Designs
Fujitsu’s CE61 is a series of high-performance, CMOS
embedded arrays featuring full support of mixed-signal
macros, as well as diffused high-speed RAMs, ROMs and a
variety of other embedded functions. The CE61 series offers
density and performance approaching standard cells, yet
provides the time-to-market advantage of gate arrays. The
E-series is optimized for pad-limited designs, and the F-series
offers a cost-effective solution for core-limited designs. A fifth
metal layer option is also available for area bump designs,
providing over 1,000 I/O pads.
Frame
Total Gates
1,584K
1,149K
784K
Total Pads
CE61E71
CE61E59
CE61E45
CE61E35
CE61E25
CE61E19
CE61E15
CE61E09
CE61E08
CE61E07
672
576
480
424
352
304
256
208
176
160
602K
403K
280K
193K
120K
80K
64K
Featuring true 3.3V internal operation, with 3.3V, 5V and
5V tolerant I/Os, the CE61 series features a very low-power
consumption of 0.32µW/gate/MHz. Potential applications
for the CE61 series include computing, graphics, communica-
tions, networking, wireless, and consumer designs.
F-series, Optimized for Core-Limited Designs
Frame
Total Gates
2,026K
1,508K
1,182K
913K
Total Pads
CE61F80
CE61F70
CE61F60
CE61F50
CE61F40
CE61F30
CE61F20
CE61F10
456
400
400
352
304
256
208
144
664K
476K
303K
132K