5秒后页面跳转
捷配首页

Datasheet > CD74HCT93M96
CD74HCT93M96 PDF预览

CD74HCT93M96

更新时间： 2024-11-03 20:19:55
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
14页 538K
描述
HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDSO14

阅读下载

中文翻译

获取价格

CD74HCT93M96 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.69
Is Samacsys：N其他特性：DIVIDE BY 2 AND DIVIDE BY 8 FUNCTIONS
计数方向：UP系列：HCT
JESD-30 代码：R-PDSO-G14长度：8.65 mm
负载电容（CL）：50 pF负载/预设输入：NO
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：20000000 Hz
最大I（ol）：0.004 A工作模式：ASYNCHRONOUS
位数：3功能数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL电源：5 V
传播延迟（tpd）：87 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：NEGATIVE EDGE
宽度：3.9 mm最小 fmax：30 MHz
Base Number Matches：1

CD74HCT93M96 数据手册

 浏览型号CD74HCT93M96的Datasheet PDF文件第2页浏览型号CD74HCT93M96的Datasheet PDF文件第3页浏览型号CD74HCT93M96的Datasheet PDF文件第4页浏览型号CD74HCT93M96的Datasheet PDF文件第5页浏览型号CD74HCT93M96的Datasheet PDF文件第6页浏览型号CD74HCT93M96的Datasheet PDF文件第7页 
CD74HC93,  
CD74HCT93  
Data sheet acquired from Harris Semiconductor  
SCHS138C  
High-Speed CMOS Logic  
4-Bit Binary Ripple Counter  
August 1997 - Revised September 2003  
Features  
Description  
• Can Be Configured to Divide By 2, 8, and 16  
• Asynchronous Master Reset  
The CD74HC93 and CD74HCT93 are high-speed silicon-gate  
CMOS devices and are pin-compatible with low power  
Schottky TTL (LSTTL). These 4-bit binary ripple counters  
consist of four master-slave flip-flops internally connected to  
provide a divide-by-two section and a divide- by-eight section.  
Each section has a separate clock input (CP0 and CP1) to  
initiate state changes of the counter on the HIGH to LOW  
[ /Title  
(CD74  
HC93,  
CD74  
HCT93  
)
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
clock transition. State changes of the Q outputs do not occur  
n
simultaneously because of internal ripple delays. Therefore,  
decoded output signals are subject to decoding spikes and  
should not be used for clocks or strobes.  
/Sub-  
ject  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
A gated AND asynchronous master reset (MR1 and MR2 is  
provided which overrides both clocks and resets (clears) all  
flip-flops.  
(High  
Speed  
CMOS  
Logic  
4-Bit  
Binary  
Ripple  
Counte  
r)  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
Because the output from the divide by two section is not  
internally connected to the succeeding stages, the device  
may be operated in various counting modes.  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
In a 4-bit ripple counter the output Q must be connected  
0
externally to input CP1. The input count pulses are applied  
to clock input CP0. Simultaneous frequency divisions of 2, 4,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
8, and 16 are performed at the Q , Q , Q , and Q outputs  
0
1
2
3
as shown in the function table. As a 3-bit ripple counter the  
input count pulses are applied to input CP1.  
Pinout  
Simultaneous frequency divisions of 2, 4, and 8 are available  
CD74HC93  
(PDIP, SOIC)  
CD74HCT93  
(PDIP)  
at the Q , Q , Q outputs. Independent use of the first flip-  
1
2
3
flop is available if the reset function coincides with the reset  
of the 3-bit ripple-through counter.  
TOP VIEW  
Ordering Information  
CP1  
MR1  
MR2  
NC  
1
2
3
4
5
6
7
14 CPO  
13 NC  
TEMP. RANGE  
o
PART NUMBER  
CD74HC93E  
( C)  
PACKAGE  
14 Ld PDIP  
12  
Q
0
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
11 Q  
3
CD74HC93M  
CD74HC93MT  
CD74HC93M96  
CD74HCT93E  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
V
10 GND  
CC  
NC  
NC  
9
8
Q
1
2
Q
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
1234567...14

中文翻译

下载PDF

与CD74HCT93M96相关器件

型号 品牌 获取价格 描述 数据表
CD74HCU04 TI

获取价格

 		High Speed CMOS Logic Hex Inverter
CD74HCU04_06 TI

获取价格

 		High-Speed CMOS Logic Hex Inverter
CD74HCU04_08 TI

获取价格

 		High-Speed CMOS Logic Hex Inverter
CD74HCU04E TI

获取价格

 		High Speed CMOS Logic Hex Inverter
CD74HCU04EE4 TI

获取价格

 		High-Speed CMOS Logic Hex Inverter
CD74HCU04EN ETC

获取价格

 		Logic IC
CD74HCU04F ETC

获取价格

 		Logic IC
CD74HCU04H ETC

获取价格

 		Hex Inverter
CD74HCU04M TI

获取价格

 		High Speed CMOS Logic Hex Inverter
CD74HCU04M96 TI

获取价格

 		High-Speed CMOS Logic Hex Inverter

与CD74HCT93M96相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证