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CD74HCT670MTE4

更新时间： 2024-01-26 09:28:33
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
14页 284K
描述
High-Speed CMOS Logic 4x4 Register File

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CD74HCT670MTE4 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.25
针数：16Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.32.00.41
风险等级：5.79Is Samacsys：N
最长访问时间：53 nsJESD-30 代码：R-PDSO-G16
长度：9.9 mm内存密度：16 bit
内存集成电路类型：STANDARD SRAM内存宽度：4
功能数量：1端子数量：16
字数：4 words字数代码：4
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：4X4
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Other Memory ICs最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

CD74HCT670MTE4 数据手册

 浏览型号CD74HCT670MTE4的Datasheet PDF文件第2页浏览型号CD74HCT670MTE4的Datasheet PDF文件第3页浏览型号CD74HCT670MTE4的Datasheet PDF文件第4页浏览型号CD74HCT670MTE4的Datasheet PDF文件第5页浏览型号CD74HCT670MTE4的Datasheet PDF文件第6页浏览型号CD74HCT670MTE4的Datasheet PDF文件第7页 
CD54HC670, CD74HC670,  
CD74HCT670  
Data sheet acquired from Harris Semiconductor  
SCHS195C  
High-Speed CMOS Logic  
4x4 Register File  
January 1998 - Revised October 2003  
Features  
Description  
• Simultaneous and Independent Read and Write  
Operations  
The ’HC670 and CD74HCT670 are 16-bit register files  
organized as 4 words x 4 bits each. Read and write address  
and enable inputs allow simultaneous writing into one location  
while reading another. Four data inputs are provided to store  
the 4-bit word. The write address inputs (WA0 and WA1)  
determine the location of the stored word in the register.  
When write enable (WE) is low the word is entered into the  
address location and it remains transparent to the data. The  
outputs will reflect the true form of the input data. When (WE)  
is high data and address inputs are inhibited. Data acquisition  
from the four registers is made possible by the read address  
inputs (RA1 and RA0). The addressed word appears at the  
output when the read enable (RE) is low. The output is in the  
high impedance state when the (RE) is high. Outputs can be  
tied together to increase the word capacity to 512 x 4 bits.  
[ /Title  
(CD74H  
C670,  
CD74H  
CT670)  
/Subject  
(High-  
Speed  
CMOS  
Logic  
4x4 Reg-  
ister  
• Expandable to 512 Words of n-Bits  
• Three-State Outputs  
• Organized as 4 Words x 4 Bits Wide  
• Buffered Inputs  
• Typical Read Time = 16ns for ’HC670 V  
CC  
= 5V, C =  
L
o
15pF, T = 25 C  
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC670F3A  
CD74HC670E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
CD74HC670M  
- 2V to 6V Operation  
CD74HC670MT  
CD74HC670M96  
CD74HCT670E  
CD74HCT670M  
CD74HCT670MT  
CD74HCT670M96  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC670  
(CERDIP)  
CD74HC670, CD74HCT670  
(PDIP, SOIC)  
TOP VIEW  
D1  
D2  
1
2
3
4
5
6
7
8
16 V  
CC  
15 D0  
D3  
14 WA0  
13 WA1  
12 WE  
11 RE  
10 Q0  
RA1  
RA0  
Q3  
Q2  
9
Q1  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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