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CD74HCT163E PDF预览

CD74HCT163E

更新时间： 2024-11-23 23:04:31
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 67K
描述
High Speed CMOS Logic Presettable Counters

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CD74HCT163E 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：1.31
Is Samacsys：N其他特性：TCO OUTPUT
计数方向：UP系列：HCT
JESD-30 代码：R-PDIP-T16JESD-609代码：e4
长度：19.3 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：20000000 Hz最大I（ol）：0.004 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT APPLICABLE电源：5 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：49 ns
传播延迟（tpd）：59 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT APPLICABLE触发器类型：POSITIVE EDGE
宽度：6.35 mm最小 fmax：20 MHz
Base Number Matches：1

CD74HCT163E 数据手册

 浏览型号CD74HCT163E的Datasheet PDF文件第2页浏览型号CD74HCT163E的Datasheet PDF文件第3页浏览型号CD74HCT163E的Datasheet PDF文件第4页浏览型号CD74HCT163E的Datasheet PDF文件第5页浏览型号CD74HCT163E的Datasheet PDF文件第6页浏览型号CD74HCT163E的Datasheet PDF文件第7页 
CD74HC161, CD74HCT161,  
CD74HC163, CD74HCT163  
Data sheet acquired from Harris Semiconductor  
SCHS154  
High Speed CMOS Logic  
Presettable Counters  
February 1998  
Features  
Description  
• CD74HC161, CD74HCT161 4-Bit Binary Counter,  
Asynchronous Reset  
The Harris CD74HC161, CD74HCT161, CD74HC163 and  
CD74HCT163 are presettable synchronous counters that  
feature look-ahead carry logic for use in high-speed  
counting applications. The CD74HC161 and CD74HCT161  
are asynchronous reset decade and binary counters,  
respectively; the CD74HC163 and CD74HCT163 devices  
decade and binary counters, respectively and are reset  
synchronously with the clock. Counting and parallel  
presetting are both accomplished synchronously with the  
negative-to-positive transition of the clock.  
[ /Title  
(CD74  
HC161  
,
CD74  
HCT16  
1,  
CD74  
HC163  
,
CD74  
HCT16  
3)  
• CD74HC163, CD74HCT163 4-Bit Binary Counter,  
Synchronous Reset  
• Synchronous Counting and Loading  
• Two Count Enable Inputs for n-Bit Cascading  
• Look-Ahead Carry for High-Speed Counting  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
A low level on the synchronous parallel enable input, SPE,  
disables counting operation and allows data at the P0 to P3  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C inputs to be loaded into the counter (provided that the  
setup and hold requirements for SPE are met).  
• Balanced Propagation Delay and Transition Times  
All counters are reset with a low level on the Master Reset  
input, MR. In the CD74HC163 and CD74HCT163 counters  
(synchronous reset types), the requirements for setup and  
hold time with respect to the clock must be met.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
/Sub-  
ject  
- 2V to 6V Operation  
Two count enables, PE and TE, in each counter are  
provided for n-bit cascading. In all counters reset action  
occurs regardless of the level of the SPE, PE and TE inputs  
(and the clock input, CP, in the CD74HC161 and  
CD74HCT161 types).  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
If a decade counter is preset to an illegal state or assumes  
an illegal state when power is applied, it will return to the  
normal sequence in one count as shown in state diagram.  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
Counte  
rs)  
/Autho  
r ()  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
The look-ahead carry feature simplifies serial cascading of  
the counters. Both count enable inputs (PE and TE) must  
be high to count. The TE input is gated with the Q outputs  
of all four stages so that at the maximum count the terminal  
count (TC) output goes high for one clock period. This TC  
pulse is used to enable the next cascaded stage.  
Ordering Information  
PKG.  
NO.  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
CD74HC161E  
CD74HC161M  
CD74HC163E  
CD74HC163M  
CD74HCT161E  
CD74HCT161M  
CD74HCT163E  
CD74HCT163M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld PDIP  
E16.3  
16 Ld SOIC M16.15  
16 Ld PDIP E16.3  
16 Ld SOIC M16.15  
16 Ld PDIP E16.3  
16 Ld SOIC M16.15  
16 Ld PDIP E16.3  
16 Ld SOIC M16.15  
Pinout  
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163  
(PDIP, SOIC)  
TOP VIEW  
MR  
CP  
P0  
1
2
3
4
5
6
7
8
16 V  
CC  
15 TC  
14 Q0  
13 Q1  
12 Q2  
11 Q3  
10 TE  
Counte  
rs,  
High  
Speed  
P1  
P2  
1. When ordering, use the entire part number. Add the suffix 96 to ob-  
tain the variant in the tape and reel.  
P3  
PE  
2. Wafer and die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or Harris  
customer service for ordering information.  
9
SPE  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1550.1  
Copyright © Harris Corporation 1998  
1
1234567...10

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CD74HCT163E 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT163M TI

完全替代

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