CD74HCT109M96G4

更新时间： 2024-01-17 11:36:00

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
16页	348K
描述
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

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中文翻译

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数据手册

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CD74HCT109M96G4 数据手册

CD54HC109, CD74HC109,

CD54HCT109, CD74HCT109

Data sheet acquired from Harris Semiconductor

SCHS140E

Dual J-K Flip-Flop with Set and Reset

Positive-Edge Trigger

March 1998 - Revised October 2003

Features

Description

• Asynchronous Set and Reset

• Schmitt Trigger Clock Inputs

The ’HC109 and ’HCT109 are dual J-K ﬂip-ﬂops with set and

reset. The ﬂip-ﬂop changes state with the positive transition

of Clock (1CP and 2CP).

[ /Title

(CD74H

C109,

CD74H

CT109)

/Subject

(Dual J-

K Flip-

Flop

• Typical f

MAX

= 54MHz at V = 5V, C = 15pF,

CC L

The ﬂip-ﬂop is set and reset by active-low S and R,

respectively. A low on both the set and reset inputs

simultaneously will force both Q and Q outputs high.

However, both set and reset going high simultaneously

results in an unpredictable output condition.

T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

TEMP. RANGE

PART NUMBER

CD54HC109F3A

CD54HCT109F3A

CD74HC109E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

16 Ld SOIC

16 Ld PDIP

16 Ld SOIC

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

with Set

and

Reset

-55 to 125

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC109M

at V

= 5V

CD74HC109MT

CD74HC109M96

CD74HCT109E

CD74HCT109M

CD74HCT109MT

CD74HCT109M96

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Pinout

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

CD54HC109, CD54HCT109

(CERDIP)

CD74HC109, CD74HCT109

(PDIP, SOIC)

TOP VIEW

16 V

15 2R

14 2J

13 2K

12 2CP

11 2S

10 2Q

1CP

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...16

中文翻译

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与CD74HCT109M96G4相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT109ME4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT109MG4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT109MT	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT109MTE4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT109MTG4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT10E	TI	获取价格	High-Speed CMOS Logic Triple 3-Input NAND Gate
CD74HCT10E	ROCHESTER	获取价格	暂无描述
CD74HCT10E	RENESAS	获取价格	NAND GATE
CD74HCT10E98	RENESAS	获取价格	IC,LOGIC GATE,3 3-INPUT NAND,HCT-CMOS,DIP,14PIN,PLASTIC
CD74HCT10EE4	TI	获取价格	High-Speed CMOS Logic Triple 3-Input NAND Gate

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