Datasheet > CD74HCT112

CD74HCT112

更新时间： 2024-11-18 23:04:27

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
8页	57K
描述
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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中文翻译

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数据手册

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CD74HCT112 数据手册

CD74HC112,

CD74HCT112

Data sheet acquired from Harris Semiconductor

SCHS141

Dual J-K Flip-Flop with Set and Reset

Negative-Edge Trigger

March 1998

at V

= 5V

Features

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

[ /Title

(CD74

HC112

CD74

HCT11

V = 0.8V (Max), V = 2V (Min)

IL IH

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

Description

The Harris CD74HC112 and CD74HCT112 utilize silicon-

gate CMOS technology to achieve operating speeds

equivalent to LSTTL parts. They exhibit the low power

consumption of standard CMOS integrated circuits, together

with the ability to drive 10 LSTTL loads.

/Sub-

ject

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

(Dual

J-K

• Fanout (Over Temperature Range)

These ﬂip-ﬂops have independent J, K, Set, Reset, and

Clock inputs and Q and Q outputs. They change state on the

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

Flip-

Flop

with

Setand

Reset

Nega-

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads negative-going transition of the clock pulse. Set and Reset

are accomplished asynchronously by low-level inputs.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

The 74HCT logic family is functionally as well as pin-

compatible with the standard 74LS logic family.

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

Ordering Information

• HC Types

TEMP. RANGE

PKG.

NO.

- 2V to 6V Operation

PART NUMBER

( C)

PACKAGE

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC112E

-55 to 125

16 Ld PDIP

E16.3

Pinout

CD74HC112, CD74HCT112

(PDIP)

TOP VIEW

1CP

16 V

15 1R

14 2R

13 2CP

12 2K

11 2J

10 2S

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1843.1

12 3 4 5 6 7 8

中文翻译

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与CD74HCT112相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT112E	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HCT112EE4	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD74HCT112EN	ETC	获取价格	Logic IC
CD74HCT112EX	RENESAS	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
CD74HCT112F	ETC	获取价格	Logic IC
CD74HCT112H	ETC	获取价格	J-K-Type Flip-Flop
CD74HCT112M	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,SOP,16PIN,PLASTIC
CD74HCT112M	ROCHESTER	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
CD74HCT112M96	RENESAS	获取价格	J-K Flip-Flop, HCT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, C
CD74HCT11E	TI	获取价格	High Speed CMOS Logic Triple 3-Input AND Gate

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