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CD74HC93

更新时间： 2024-11-18 23:00:39
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德州仪器 - TI 计数器
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7页 50K
描述
High Speed CMOS Logic 4-Bit Binary Ripple Counter

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CD74HC93 数据手册

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CD74HC93,  
CD74HCT93  
Data sheet acquired from Harris Semiconductor  
SCHS138  
High Speed CMOS Logic  
August 1997  
4-Bit Binary Ripple Counter  
Features  
Description  
• Can Be Configured to Divide By 2, 8, and 16  
• Asynchronous Master Reset  
The Harris CD74HC93 and CD74HCT93 are high speed  
silicon-gate CMOS devices and are pin-compatible with low  
power Schottky TTL (LSTTL). These 4-bit binary ripple  
counters consist of four master-slave flip-flops internally  
connected to provide a divide-by-two-section and a divid- by-  
eight-section. Each section has a separate clock input (CP0  
and CP1) to innate state changes of the counter on the HIGH  
to LOW clock transition. Sate changes of the Qn outputs do  
not occur simultaneously because of internal ripple delays.  
Therefore, decoded output signals are subject to decoding  
spikes and should not be used for clocks or strobes.  
[ /Title  
(CD74  
HC93,  
CD74  
HCT93  
)
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
A gated AND asynchronous master reset (MR1 and MR2 is  
provided which overrides both clocks and resets (clears) all  
flip-flops.  
(High  
Speed  
CMOS  
Logic  
4-Bit  
Binary  
Ripple  
Counte  
r)  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
Because the output from the divide by two section is not  
internally connected to the succeeding stages, the device  
may be operated in various counting modes.  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
In a 4-bit ripple counter the output Q0 must be connected  
externally to input CP1. The input count pulses are applied  
to clock input CP0. Simultaneous frequency divisions of 2, 4,  
8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs  
as shown in the function table. As a 3-bit ripple counter the  
input count pulses are applied to input CP1.  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
Pinout  
Simultaneous frequency divisions of 2, 4, and 8 are available  
CD74HC93, CD74HCT93  
(PDIP, SOIC)  
at the Q , Q , Q outputs. Independent use of the first flip-  
1
2
3
flop is available if the reset function coincides with the reset  
TOP VIEW  
of the 3-bit ripple-through counter.  
CP1  
1
2
3
4
5
6
7
14 CPO  
13 NC  
Ordering Information  
MR1  
MR2  
NC  
TEMP. RANGE  
PKG.  
NO.  
12  
Q
0
o
PART NUMBER  
CD74HC93E  
CD74HCT93E  
CD74HC93M  
CD74HCT93M  
NOTES:  
( C)  
PACKAGE  
14 Ld PDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
11 Q  
3
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
E14.3  
V
10 GND  
CC  
E14.3  
NC  
NC  
9
8
Q
1
2
Q
M14.15  
M14.15  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Die for this part number is available which meets all electrical  
specifications. Please contact your local sales office or Harris  
customer service for ordering information.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1849.1  
Copyright © Harris Corporation 1997  
1
1234567

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