Datasheet > CD74HC93_08

CD74HC93_08

更新时间： 2024-02-11 18:35:00

品牌	Logo	应用领域
德州仪器 - TI		计数器
页数	文件大小	规格书
13页	382K
描述
High-Speed CMOS Logic 4-Bit Binary Ripple Counter

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数据手册

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CD74HC93_08 数据手册

CD74HC93,

CD74HCT93

Data sheet acquired from Harris Semiconductor

SCHS138C

High-Speed CMOS Logic

4-Bit Binary Ripple Counter

August 1997 - Revised September 2003

Features

Description

• Can Be Conﬁgured to Divide By 2, 8, and 16

• Asynchronous Master Reset

The CD74HC93 and CD74HCT93 are high-speed silicon-gate

CMOS devices and are pin-compatible with low power

Schottky TTL (LSTTL). These 4-bit binary ripple counters

consist of four master-slave flip-flops internally connected to

provide a divide-by-two section and a divide- by-eight section.

Each section has a separate clock input (CP0 and CP1) to

initiate state changes of the counter on the HIGH to LOW

[ /Title

(CD74

HC93,

CD74

HCT93

)

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

clock transition. State changes of the Q outputs do not occur

simultaneously because of internal ripple delays. Therefore,

decoded output signals are subject to decoding spikes and

should not be used for clocks or strobes.

/Sub-

ject

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

A gated AND asynchronous master reset (MR1 and MR2 is

provided which overrides both clocks and resets (clears) all

ﬂip-ﬂops.

(High

Speed

CMOS

Logic

4-Bit

Binary

Ripple

Counte

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

at V

= 5V

Because the output from the divide by two section is not

internally connected to the succeeding stages, the device

may be operated in various counting modes.

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

In a 4-bit ripple counter the output Q must be connected

externally to input CP1. The input count pulses are applied

to clock input CP0. Simultaneous frequency divisions of 2, 4,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

8, and 16 are performed at the Q , Q , Q , and Q outputs

as shown in the function table. As a 3-bit ripple counter the

input count pulses are applied to input CP1.

Pinout

Simultaneous frequency divisions of 2, 4, and 8 are available

CD74HC93

(PDIP, SOIC)

CD74HCT93

(PDIP)

at the Q , Q , Q outputs. Independent use of the ﬁrst ﬂip-

ﬂop is available if the reset function coincides with the reset

of the 3-bit ripple-through counter.

TOP VIEW

Ordering Information

CP1

MR1

MR2

14 CPO

13 NC

TEMP. RANGE

PART NUMBER

CD74HC93E

( C)

PACKAGE

14 Ld PDIP

-55 to 125

11 Q

CD74HC93M

CD74HC93MT

CD74HC93M96

CD74HCT93E

14 Ld SOIC

14 Ld PDIP

10 GND

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...13

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与CD74HC93_08相关器件

型号	品牌	获取价格	描述	数据表
CD74HC93E	TI	获取价格	High Speed CMOS Logic 4-Bit Binary Ripple Counter
CD74HC93E	RENESAS	获取价格	IC,COUNTER,UP,4-BIT BINARY,HC-CMOS,DIP,14PIN,PLASTIC
CD74HC93EE4	TI	获取价格	High-Speed CMOS Logic 4-Bit Binary Ripple Counter
CD74HC93EN	ETC	获取价格	Logic IC
CD74HC93EX	RENESAS	获取价格	HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, PDIP14
CD74HC93F	ETC	获取价格	Logic IC
CD74HC93H	ETC	获取价格	Asynchronous Up Counter
CD74HC93M	TI	获取价格	High Speed CMOS Logic 4-Bit Binary Ripple Counter
CD74HC93M	RENESAS	获取价格	IC,COUNTER,UP,4-BIT BINARY,HC-CMOS,SOP,14PIN,PLASTIC
CD74HC93M96	RENESAS	获取价格	IC,COUNTER,UP,4-BIT BINARY,HC-CMOS,SOP,14PIN,PLASTIC

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