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CD74HC93_06

更新时间： 2024-11-23 05:09:11
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德州仪器 - TI 计数器
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10页 202K
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High-Speed CMOS Logic 4-Bit Binary Ripple Counter

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CD74HC93_06 数据手册

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CD74HC93,  
CD74HCT93  
Data sheet acquired from Harris Semiconductor  
SCHS138C  
High-Speed CMOS Logic  
4-Bit Binary Ripple Counter  
August 1997 - Revised September 2003  
Features  
Description  
• Can Be Configured to Divide By 2, 8, and 16  
• Asynchronous Master Reset  
The CD74HC93 and CD74HCT93 are high-speed silicon-gate  
CMOS devices and are pin-compatible with low power  
Schottky TTL (LSTTL). These 4-bit binary ripple counters  
consist of four master-slave flip-flops internally connected to  
provide a divide-by-two section and a divide- by-eight section.  
Each section has a separate clock input (CP0 and CP1) to  
initiate state changes of the counter on the HIGH to LOW  
[ /Title  
(CD74  
HC93,  
CD74  
HCT93  
)
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
clock transition. State changes of the Q outputs do not occur  
n
simultaneously because of internal ripple delays. Therefore,  
decoded output signals are subject to decoding spikes and  
should not be used for clocks or strobes.  
/Sub-  
ject  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
A gated AND asynchronous master reset (MR1 and MR2 is  
provided which overrides both clocks and resets (clears) all  
flip-flops.  
(High  
Speed  
CMOS  
Logic  
4-Bit  
Binary  
Ripple  
Counte  
r)  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
Because the output from the divide by two section is not  
internally connected to the succeeding stages, the device  
may be operated in various counting modes.  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
In a 4-bit ripple counter the output Q must be connected  
0
externally to input CP1. The input count pulses are applied  
to clock input CP0. Simultaneous frequency divisions of 2, 4,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
8, and 16 are performed at the Q , Q , Q , and Q outputs  
0
1
2
3
as shown in the function table. As a 3-bit ripple counter the  
input count pulses are applied to input CP1.  
Pinout  
Simultaneous frequency divisions of 2, 4, and 8 are available  
CD74HC93  
(PDIP, SOIC)  
CD74HCT93  
(PDIP)  
at the Q , Q , Q outputs. Independent use of the first flip-  
1
2
3
flop is available if the reset function coincides with the reset  
of the 3-bit ripple-through counter.  
TOP VIEW  
Ordering Information  
CP1  
MR1  
MR2  
NC  
1
2
3
4
5
6
7
14 CPO  
13 NC  
TEMP. RANGE  
o
PART NUMBER  
CD74HC93E  
( C)  
PACKAGE  
14 Ld PDIP  
12  
Q
0
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
11 Q  
3
CD74HC93M  
CD74HC93MT  
CD74HC93M96  
CD74HCT93E  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
V
10 GND  
CC  
NC  
NC  
9
8
Q
1
2
Q
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
1234567...10

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