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CD74HC4017-EP

更新时间： 2024-11-23 12:55:11
品牌 Logo 应用领域
德州仪器 - TI 计数器输出元件
页数 文件大小 规格书
15页 618K
描述
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS

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中文翻译

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CD74HC4017-EP 数据手册

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SCLS550 − DECEMBER 2003  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
Fanout (Over Temperature Range)  
− Standard Outputs . . . 10 LSTTL Loads  
− Bus Driver Outputs . . . 15 LSTTL Loads  
D
D
Extended Temperature Performance of  
−40°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
Balanced Propagation Delay and Transition  
Times  
Significant Power Reduction Compared to  
LSTTL Logic ICs  
D
D
D
D
D
D
D
Enhanced Product-Change Notification  
D
V
Voltage = 2 V to 6 V  
CC  
†
Qualification Pedigree  
D
High Noise Immunity N or N = 30% of  
IL  
IH  
V
, V  
= 5 V  
Fully Static Operation  
Buffered Inputs  
CC CC  
M OR PW PACKAGE  
(TOP VIEW)  
Common Reset  
Positive Edge Clocking  
5
1
2
3
4
5
6
7
8
16  
V
CC  
1
15 MR  
14 CP  
Typical f  
= 60 MHz at V  
= 5 V,  
max  
CC  
0
C = 15 pF, T = 25°C  
L
A
13  
12  
11  
10  
9
†
2
CE  
TC  
9
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
6
7
3
4
GND  
8
description/ordering information  
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each  
of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of  
the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and  
can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting  
when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded  
outputs, except output 0, to low.  
The device can drive up to ten low-power Schottky equivalent loads.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − M  
Tape and reel  
CD74HC4017QM96EP  
HC4017E  
−40°C to 125°C  
TSSOP − PW Tape and reel  
CD74HC4017QPWREP HC4017E  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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CD74HC4017-EP 替代型号

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