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CD74HC4002M96E4 PDF预览

CD74HC4002M96E4

更新时间: 2024-11-23 23:00:39
品牌 Logo 应用领域
德州仪器 - TI
页数 文件大小 规格书
12页 343K
描述
High-Speed CMOS Logic Dual 4-Input NOR Gate

CD74HC4002M96E4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.11系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:2
输入次数:4端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):150 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

CD74HC4002M96E4 数据手册

 浏览型号CD74HC4002M96E4的Datasheet PDF文件第2页浏览型号CD74HC4002M96E4的Datasheet PDF文件第3页浏览型号CD74HC4002M96E4的Datasheet PDF文件第4页浏览型号CD74HC4002M96E4的Datasheet PDF文件第5页浏览型号CD74HC4002M96E4的Datasheet PDF文件第6页浏览型号CD74HC4002M96E4的Datasheet PDF文件第7页 
CD54HC4002, CD74HC4002  
Data sheet acquired from Harris Semiconductor  
SCHS197E  
High-Speed CMOS Logic  
Dual 4-Input NOR Gate  
August 1997 - Revised October 2003  
Features  
Description  
• Typical Propagation Delay = 8ns at V  
o
= 5V,  
The ’HC4002 logic gate utilizes silicon gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The ’HC4002 logic family is functional as well  
as pin compatible with the standard LS logic family.  
CC  
C = 15pF, T = 25 C  
L
A
[ /Title  
(CD74H  
C4002)  
/Subject  
(High  
Speed  
CMOS  
Logic  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC4002F3A  
CD74HC4002E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Dual 4-  
Input  
NOR  
• HC Types  
- 2V to 6V Operation  
CD74HC4002M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
- High Noise Immunity: N = 30%, N = 30%of V  
IL IH  
at  
CC  
V
= 5V  
CD74HC4002MT  
CD74HC4002M96  
CD74HC4002NSR  
CD74HC4002PW  
CD74HC4002PWR  
CD74HC4002PWT  
CC  
Gate)  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld TSSOP  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Pinout  
CD54HC4002  
(CERDIP)  
CD74HC4002  
(PDIP, SOIC, SOP, TSSOP)  
TOP VIEW  
1Y  
1A  
1
2
3
4
5
6
7
14 V  
CC  
13 2Y  
12 2D  
11 2C  
10 2B  
1B  
1C  
1D  
NC  
GND  
9
8
2A  
NC  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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