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CD54HCT373F3A PDF预览

CD54HCT373F3A

更新时间： 2024-11-19 21:57:47
品牌 Logo 应用领域
德州仪器 - TI 锁存器逻辑集成电路输出元件驱动
页数 文件大小 规格书
10页 318K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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CD54HCT373F3A 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.19控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：HCT
JESD-30 代码：R-GDIP-T20长度：24.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：0.08 mA
Prop。Delay @ Nom-Sup：48 ns传播延迟（tpd）：53 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：6.92 mmBase Number Matches：1

CD54HCT373F3A 数据手册

 浏览型号CD54HCT373F3A的Datasheet PDF文件第2页浏览型号CD54HCT373F3A的Datasheet PDF文件第3页浏览型号CD54HCT373F3A的Datasheet PDF文件第4页浏览型号CD54HCT373F3A的Datasheet PDF文件第5页浏览型号CD54HCT373F3A的Datasheet PDF文件第6页浏览型号CD54HCT373F3A的Datasheet PDF文件第7页 
CD54HCT373, CD74HCT373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS453B – FEBRUARY 2001 – REVISED MAY 2003  
CD54HCT373 . . . F PACKAGE  
CD74HCT373 . . . E OR M PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Wide Operating Temperature Range of  
–55°C to 125°C  
Balanced Propagation Delays and  
Transition Times  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
8Q  
8D  
7D  
Standard Outputs Drive Up To 10 LS-TTL  
Loads  
16 7Q  
15 6Q  
Significant Power Reduction Compared to  
LS-TTL Logic ICs  
14  
13  
12  
11  
6D  
5D  
5Q  
LE  
Inputs Are TTL-Voltage Compatible  
description/ordering information  
GND  
The ’HCT373 devices are octal transparent  
D-type latches. When the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is low, the Q outputs are latched at the  
logic levels of the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74HCT373E  
CD74HCT373M  
CD74HCT373M96  
CD54HCT373F3A  
CD74HCT373E  
–55°C to 125°C  
SOIC – M  
HCT373M  
Tape and reel  
Tube  
CDIP – F  
CD54HCT373F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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CD54HCT373F3A 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT373M TI

完全替代

 High Speed CMOS Logic Octal Transparent Latch, Three-State Output
CD74HCT373E TI

完全替代

 High Speed CMOS Logic Octal Transparent Latch, Three-State Output
JM38510/65453BRA TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

与CD54HCT373F3A相关器件

型号 品牌 获取价格 描述 数据表
CD54HCT373H RENESAS

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 		CD54HCT373H
CD54HCT373H/3 RENESAS

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 		HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, UUC20
CD54HCT373H/3A RENESAS

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 		HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, UUC20
CD54HCT373M ETC

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 		Logic IC
CD54HCT374 TI

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 		High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered
CD54HCT374E ETC

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 		Logic IC
CD54HCT374EN ETC

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 		Logic IC
CD54HCT374F RENESAS

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 		HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20
CD54HCT374F/3 RENESAS

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 		HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20
CD54HCT374F/3A RENESAS

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 		IC HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, Bus Driver/Transceiver

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