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CD54HCT02F PDF预览

CD54HCT02F

更新时间: 2024-11-18 22:40:23
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路
页数 文件大小 规格书
10页 265K
描述
High-Speed CMOS Logic Quad Two-Input NOR Gate

CD54HCT02F 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.29
系列:HCTJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:32 ns传播延迟(tpd):32 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.67 mmBase Number Matches:1

CD54HCT02F 数据手册

 浏览型号CD54HCT02F的Datasheet PDF文件第2页浏览型号CD54HCT02F的Datasheet PDF文件第3页浏览型号CD54HCT02F的Datasheet PDF文件第4页浏览型号CD54HCT02F的Datasheet PDF文件第5页浏览型号CD54HCT02F的Datasheet PDF文件第6页浏览型号CD54HCT02F的Datasheet PDF文件第7页 
CD54HC02, CD74HC02,  
CD54HCT02, CD74HCT02  
Data sheet acquired from Harris Semiconductor  
SCHS125C  
High-Speed CMOS Logic  
Quad Two-Input NOR Gate  
March 1998 - Revised September 2003  
Features  
Description  
• Buffered Inputs  
The ’HC02 and ’HCT02 logic gates utilize silicon-gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The HCT logic family is functionally pin  
compatible with the standard LS logic family.  
• Typical Propagation Delay: 7ns at V  
o
= 5V,  
[ /Title  
(CD74H  
C02,  
CD74H  
CT02)  
/Subject  
(High  
Speed  
CMOS  
Logic  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
o
PART NUMBER  
CD54HC02F3A  
CD54HCT02F3A  
CD74HC02E  
TEMP. RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
Quad  
Two-  
- 2V to 6V Operation  
CD74HC02M  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
CD74HC02MT  
CD74HC02M96  
CD74HCT02E  
CD74HCT02M  
CD74HCT02MT  
CD74HCT02M96  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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