CD54HC03, CD74HC03,
CD54HCT03, CD74HCT03
Data sheet acquired from Harris Semiconductor
SCHS126D
High-Speed CMOS Logic
February 1998 - Revised September 2003
Quad 2-Input NAND Gate with Open Drain
Features
Description
• Buffered Inputs
The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The HCT logic family is functionally as well as
pin compatible with the standard LS logic family.
• Typical Propagation Delay: 8ns at V
o
= 5V,
[ /Title
(CD74H
C03,
CC
C = 15pF, T = 25 C
L
A
• Output Pull-up to 10V
CD74H
CT03)
/Subject
(High
• Fanout (Over Temperature Range)
These open drain NAND gates can drive into resistive loads
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
to output voltages as high as 10V. Minimum values of R
required versus load voltage are shown in Figure 2.
L
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
Speed
CMOS
Logic
Quad 2-
Input
TEMP. RANGE
o
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
CD54HC03F3A
CD54HCT03F3A
CD74HC03E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC03M
• HCT Types
CD74HC03MT
CD74HC03M96
CD74HCT03E
CD74HCT03M
CD74HCT03MT
CD74HCT03M96
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC03, CD54HCT03
(CERDIP)
CD74HC03, CD74HCT03
(PDIP, SOIC)
TOP VIEW
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
1Y
2A
2B
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1