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CD54HC670_07

更新时间: 2024-11-23 05:09:03
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德州仪器 - TI /
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17页 351K
描述
High-Speed CMOS Logic 4x4 Register File

CD54HC670_07 数据手册

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CD54HC670, CD74HC670,  
CD74HCT670  
Data sheet acquired from Harris Semiconductor  
SCHS195C  
High-Speed CMOS Logic  
4x4 Register File  
January 1998 - Revised October 2003  
Features  
Description  
• Simultaneous and Independent Read and Write  
Operations  
The ’HC670 and CD74HCT670 are 16-bit register files  
organized as 4 words x 4 bits each. Read and write address  
and enable inputs allow simultaneous writing into one location  
while reading another. Four data inputs are provided to store  
the 4-bit word. The write address inputs (WA0 and WA1)  
determine the location of the stored word in the register.  
When write enable (WE) is low the word is entered into the  
address location and it remains transparent to the data. The  
outputs will reflect the true form of the input data. When (WE)  
is high data and address inputs are inhibited. Data acquisition  
from the four registers is made possible by the read address  
inputs (RA1 and RA0). The addressed word appears at the  
output when the read enable (RE) is low. The output is in the  
high impedance state when the (RE) is high. Outputs can be  
tied together to increase the word capacity to 512 x 4 bits.  
[ /Title  
(CD74H  
C670,  
CD74H  
CT670)  
/Subject  
(High-  
Speed  
CMOS  
Logic  
4x4 Reg-  
ister  
• Expandable to 512 Words of n-Bits  
• Three-State Outputs  
• Organized as 4 Words x 4 Bits Wide  
• Buffered Inputs  
• Typical Read Time = 16ns for ’HC670 V  
CC  
= 5V, C =  
L
o
15pF, T = 25 C  
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC670F3A  
CD74HC670E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
CD74HC670M  
- 2V to 6V Operation  
CD74HC670MT  
CD74HC670M96  
CD74HCT670E  
CD74HCT670M  
CD74HCT670MT  
CD74HCT670M96  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC670  
(CERDIP)  
CD74HC670, CD74HCT670  
(PDIP, SOIC)  
TOP VIEW  
D1  
D2  
1
2
3
4
5
6
7
8
16 V  
CC  
15 D0  
D3  
14 WA0  
13 WA1  
12 WE  
11 RE  
10 Q0  
RA1  
RA0  
Q3  
Q2  
9
Q1  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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