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CD54HC4511 PDF预览

CD54HC4511

更新时间: 2024-11-27 05:09:03
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器锁存器
页数 文件大小 规格书
17页 428K
描述
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS

CD54HC4511 数据手册

 浏览型号CD54HC4511的Datasheet PDF文件第2页浏览型号CD54HC4511的Datasheet PDF文件第3页浏览型号CD54HC4511的Datasheet PDF文件第4页浏览型号CD54HC4511的Datasheet PDF文件第5页浏览型号CD54HC4511的Datasheet PDF文件第6页浏览型号CD54HC4511的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢈꢃ ꢂꢅꢅ  
ꢉꢀꢁ ꢊꢈꢋ ꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑ ꢒꢈ ꢀꢄꢓ ꢁꢍꢀꢋ ꢁꢍ ꢔꢓ ꢁꢔ ꢕ ꢖꢍ ꢔ ꢌ  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003  
CD54HC4511 . . . F PACKAGE  
D
D
2-V to 6-V V  
Operation (’HC4511)  
CC  
CD74HC4511 . . . E, M, OR PW PACKAGE  
CD74HCT4511 . . . E PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
(CD74HCT4511)  
Operation  
CC  
D
High-Output Sourcing Capability  
− 7.5 mA at 4.5 V (CD74HCT4511)  
− 10 mA at 6 V (’HC4511)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
f
D
D
BCD  
Inputs  
CC  
1
2
g
a
b
c
d
e
LT  
BL  
LE  
D
D
D
D
D
Input Latches for BCD Code Storage  
Lamp Test and Blanking Capability  
7-Segment  
Outputs  
Balanced Propagation Delays and  
Transition Times  
D
BCD  
Inputs  
3
D
0
Significant Power Reduction Compared to  
LSTTL Logic ICs  
GND  
’HC4511  
− High Noise Immunity,  
DISPLAY  
N
or N = 30% of V  
at V  
= 5 V  
IL  
IH  
CC  
CC  
D
CD74HCT4511  
− Direct LSTTL Input Logic Compatibility,  
= 0.8 V Maximum, V = 2 V Minimum  
0
1
2
3
4
5
6
7
8
9
a
V
IL  
IH  
f
g
b
− CMOS Input Compatibility, I 1 µA  
I
at V , V  
e
c
OL OH  
d
description/ordering information  
The CD54HC4511, CD74HC4511, and CD74HCT4511 are BCD-to-7 segment latch/decoder/drivers with four  
address inputs (D −D ), an active-low blanking (BL) input, lamp-test (LT) input, and a latch-enable (LE) input  
0
3
that, when high, enables the latches to store the BCD inputs. When LE is low, the latches are disabled, making  
the outputs transparent to the BCD inputs.  
These devices have standard-size output transistors, but are capable of sourcing (at standard V  
to 7.5 mA at 4.5 V. The HC types can supply up to 10 mA at 6 V.  
levels) up  
OH  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
CD74HC4511E  
CD74HC4511E  
CD74HCT4511E  
PDIP − E  
SOIC − M  
Tube of 25  
CD74HCT4511E  
CD74HC4511M  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 250  
Tube of 25  
CD74HC4511M96  
CD74HC4511MT  
CD74HC4511PWR  
CD74HC4511PWT  
CD54HC4511F3A  
HC4511M  
−55°C to 125°C  
TSSOP − PW  
CDIP − F  
HJ4511  
CD54HC4511F3A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢋ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢏꢕ ꢑꢊ ꢗꢔ ꢯ ꢊꢰꢱꢂ ꢰꢂꢆ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢋ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢆ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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