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CD54ACT280F3A PDF预览

CD54ACT280F3A

更新时间: 2024-09-14 22:40:23
品牌 Logo 应用领域
德州仪器 - TI 运算电路逻辑集成电路
页数 文件大小 规格书
10页 260K
描述
9-Bit Odd/Even Parity Generator/Checker

CD54ACT280F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.42其他特性:ODD/EVEN PARITY GENERATOR
系列:ACTJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:PARITY GENERATOR/CHECKER最大I(ol):0.075 A
位数:9功能数量:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):0.08 mAProp。Delay @ Nom-Sup:19.6 ns
传播延迟(tpd):21.6 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.67 mm
Base Number Matches:1

CD54ACT280F3A 数据手册

 浏览型号CD54ACT280F3A的Datasheet PDF文件第2页浏览型号CD54ACT280F3A的Datasheet PDF文件第3页浏览型号CD54ACT280F3A的Datasheet PDF文件第4页浏览型号CD54ACT280F3A的Datasheet PDF文件第5页浏览型号CD54ACT280F3A的Datasheet PDF文件第6页浏览型号CD54ACT280F3A的Datasheet PDF文件第7页 
CD54/74AC280,  
CD54/74ACT280  
Data sheet acquired from Harris Semiconductor  
SCHS250A  
August 1998 - Revised May 2000  
9-Bit Odd/Even Parity Generator/Checker  
data inputs is HIGH. Odd parity is indicated (O output is  
HIGH) when an odd number of data inputs is HIGH. Parity  
checking for words larger than nine bits can be accom-  
plished by tying the E output to any input of an additional  
’AC280, ’ACT280 parity checker.  
Features  
• Buffered Inputs  
• Typical Propagation Delay  
o
- 10ns at V  
= 5V, T = 25 C, C = 50pF  
A L  
CC  
• Exceeds 2kV ESD Protection per MIL-STD-883,  
Method 3015  
Ordering Information  
PART  
NUMBER  
TEMP.  
RANGE ( C)  
• SCR-Latchup-Resistant CMOS Process and Circuit  
Design  
o
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
CD54AC280F3A  
CD74AC280E  
-55 to 125  
• Speed of Bipolar FAST™/AS/S with Significantly  
Reduced Power Consumption  
o
0 to 70 C, -40 to 85,  
-55 to 125  
• Balanced Propagation Delays  
o
CD74AC280M  
0 to 70 C, -40 to 85,  
14 Ld SOIC  
• AC Types Feature 1.5V to 5.5V Operation and  
Balanced Noise Immunity at 30% of the Supply  
-55 to 125  
CD54ACT280F3A  
CD74ACT280E  
-55 to 125  
14 Ld CERDIP  
14 Ld PDIP  
o
±24mA Output Drive Current  
- Fanout to 15 FAST™ ICs  
0 to 70 C, -40 to 85,  
-55 to 125  
o
- Drives 50Transmission Lines  
CD74ACT280M  
NOTES:  
0 to 70 C, -40 to 85,  
14 Ld SOIC  
-55 to 125  
Description  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
The ’AC280 and ’ACT280 are 9-bit odd/even parity genera-  
tor/checkers that utilize Advanced CMOS Logic technology.  
Both even and odd parity outputs are available for checking  
or generating parity for words up to nine bits long. Even par-  
ity is indicated (E output is HIGH) when an even number of  
2. Wafer and die for this part number is available which meets all elec-  
trical specifications. Please contact your local TI sales office or cus-  
tomer service for ordering information.  
Pinout  
Functional Diagram  
CD54AC280, CD54ACT280  
(CERDIP)  
CD74AC280, CD74ACT280  
(PDIP, SOIC)  
8
I0  
TOP VIEW  
9
I1  
10  
I2  
I3  
5
6
I6  
I7  
1
2
3
4
5
6
7
14 V  
CC  
EVEN  
ODD  
11  
12  
13  
1
13 I5  
12 I4  
11 I3  
10 I2  
NC  
I8  
I4  
I5  
I6  
E  
O  
GND  
9
8
I1  
I0  
2
4
I7  
I8  
GND = 7  
= 14  
V
CC  
NC = 3  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a Trademark of Fairchild Semiconductor.  
1
Copyright © 2000, Texas Instruments Incorporated  

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