Datasheet > CD4536BMS

CD4536BMS

更新时间： 2024-11-26 22:54:23

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
13页	149K
描述
CMOS Programmable Timer

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CD4536BMS 数据手册

CD4536BMS

CMOS Programmable Timer

December 1992

Features

Description

• High Voltage Type (20V Rating)

• 24 Flip-Flop Stage - Counts from 2⁰to 2²⁴

• Last 16 Stages Selectable by BCD Select Code

• Bypass Input Allows Bypassing First 8 Stages

• On-Chip RC Oscillator Provision

• Clock Inhibit Input

CD4536BMS is a programmable timer consisting of 24 ripple

binary counter stages. The salient feature of this device is its

ﬂexibility. The device can count from 1 to 2²⁴or the ﬁrst 8

stages can be bypassed to allow an output, selectable by a

4-bit code, from any one of the remaining 16 stages. It can

be driven by an external clock or an RC oscillator that can be

constructed using on-chip components. Input IN1 serves as

either the external clock input or the input to the on-chip RC

oscillator. OUT1 and OUT2 are connection terminals for the

external RC components. In addition, an on-chip monostable

circuit is provided to allow a variable pulse width output. Var-

ious timing functions can be achieved using combinations of

these capabilities.

• Schmitt Trigger in clock Line Permits Operation with

Very Long Rise and Fall Times

• On-Chip Monostable Output Provision

• Typical fCL = 3MHz at VDD = 10V

• Test Mode Allows Fast Test Sequence

• Set and Reset Inputs

A logic 1 on the 8-BYPASS input enables a bypass of the

ﬁrst 8 stages and makes stage 9 the ﬁrst counter stage of

the last 16 stages. Selection of 1 of 16 outputs is accom-

plished by the decoder and the BCD inputs A, B, C and D.

MONO IN is the timing input for the on-chip monostable

oscillator. Grounding of the MONO IN terminal through a

resistor of 10kΩ or higher, disables the one-shot circuit and

connects the decoder directly to the DECODE OUT terminal.

A resistor to VDD and a capacitor to ground from the MONO

IN terminal enables the one-shot circuit and controls its

pulse width.

• Capable of Driving Two Low Power TTL Loads, One

Lower Power Schottky Load, or Two HTL Loads Over

the Rated Temperature Range

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized, Symmetrical Output Characteristics

A fast test mode is enabled by a logic 1 on 8-BYPASS, SET,

and RESET. This mode divides the 24-stage counter into

three 8-stage sections to facilitate a fast test sequence.

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

The CD4536BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4X

H1F

H6W

Functional Diagram

Pinout

CD4536BMS

TOP VIEW

CLOCK

INHIBIT

IN 1

OSC

INHIBIT

SET

RESET

16 VDD

8-BYPASS

15 MONO IN

14 OSC INHIBIT

13 DECODE OUT

12 D

IN 1

OUT 1

BINARY

SELECT

OUT 2

8-BYPASS

CLOCK INHIBIT

VSS

BINARY

SELECT

DECODE

OUT

10 B

SET

RESET

VSS = 8

VDD = 16

MONO IN

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3345

7-1236

12 3 4 5 6 7...13

中文翻译

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