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CD4512BCJ PDF预览

CD4512BCJ

更新时间: 2024-11-21 12:59:15
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
6页 145K
描述
IC 4000/14000/40000 SERIES, 8 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16, Multiplexer/Demultiplexer

CD4512BCJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.11
系列:4000/14000/40000JESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
功能数量:1输入次数:8
输出次数:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V传播延迟(tpd):750 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

CD4512BCJ 数据手册

 浏览型号CD4512BCJ的Datasheet PDF文件第2页浏览型号CD4512BCJ的Datasheet PDF文件第3页浏览型号CD4512BCJ的Datasheet PDF文件第4页浏览型号CD4512BCJ的Datasheet PDF文件第5页浏览型号CD4512BCJ的Datasheet PDF文件第6页 
February 1988  
CD4512BM/CD4512BC 8-Channel Buffered Data Selector  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
The CD4512BM/CD4512BC buffered 8-channel data selec-  
tor is a complementary MOS (CMOS) circuit constructed  
with N- and P-channel enhancement mode transistors. This  
data selector is primarily used as a digital signal multiplexer  
selecting 1 of 8 inputs and routing the signal to a TRI-  
Y
High noise immunity  
DD  
Y
TRI-STATE output  
Y
Low quiescent power dissipation  
0.25 mW/package  
@
e
5.0V  
(typ.)  
V
CC  
STATE output. A high level at the Inhibit input forces a low  
É
Y
Plug-in replacement for Motorola MC14512  
level at the output. A high level at the Output Enable (OE)  
input forces the output into the TRI-STATE condition. Low  
levels at both the Inhibit and (OE) inputs allow normal oper-  
ation.  
Connection Diagram and Truth Table  
Dual-In-Line Package  
Order Number CD4512B  
TL/F/5993–1  
Top View  
Address Inputs  
Control Inputs  
Output  
Z
C
B
A
Inhibit  
OE  
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
j
0
0
0
0
0
0
0
0
0
1
X0  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
j
j
j
j
j
j
Hi-Z  
e
j
Don’t care  
e
Hi-Z  
TRI-STATE condition  
e
Xn  
Data at input n  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/5993  
RRD-B30M105/Printed in U. S. A.  

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