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CD4075BFMSR PDF预览

CD4075BFMSR

更新时间: 2024-11-19 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路触发器
页数 文件大小 规格书
10页 116K
描述
4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14

CD4075BFMSR 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:FRIT SEALED, DIP-14
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.71
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:9.585 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.00036 A
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:338 ns传播延迟(tpd):338 ns
认证状态:Not Qualified施密特触发器:NO
筛选级别:MIL-PRF-38535 Class V座面最大高度:5.33 mm
子类别:Gates标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V宽度:7.62 mm
Base Number Matches:1

CD4075BFMSR 数据手册

 浏览型号CD4075BFMSR的Datasheet PDF文件第2页浏览型号CD4075BFMSR的Datasheet PDF文件第3页浏览型号CD4075BFMSR的Datasheet PDF文件第4页浏览型号CD4075BFMSR的Datasheet PDF文件第5页浏览型号CD4075BFMSR的Datasheet PDF文件第6页浏览型号CD4075BFMSR的Datasheet PDF文件第7页 
CD4071BMS, CD4072BMS  
CD4075BMS  
CMOS OR Gate  
December 1992  
Features  
Pinout  
CD4071BMS  
TOP VIEW  
• High-Voltage Types (20V Rating)  
• CD4071BMS Quad 2-Input OR Gate  
• CD4072BMS Dual 4-Input OR Gate  
• CD4075BMS Triple 3-Input OR Gate  
A
1
2
3
4
5
6
7
14 VDD  
B
J = A + B  
K = C + C  
C
13  
12  
H
G
• Medium Speed Operation:  
- tPHL, tPLH = 60ns (typ) at 10V  
11 M = G + H  
10 L = E + F  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
D
9
8
F
E
VSS  
• Standardized Symmetrical Output Characteristics  
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
CD4072BMS  
TOP VIEW  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• 5V, 10V and 15V Parametric Ratings  
J = A + B + C + D  
1
2
3
4
5
6
7
14 VDD  
A
B
13 K = E +F + G + H  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
12  
11  
10  
9
H
C
G
F
D
Description  
NC  
VSS  
E
CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-  
vide the system designer with direct implementation of the  
positive-logic OR function and supplement the existing fam-  
ily of CMOS gates.  
8
NC  
NC = NO CONNECTION  
The CD4071BMS, CD4072BMS and CD4075BMS are supplied  
in these 14 lead outline packages:  
CD4075BMS  
TOP VIEW  
Braze Seal DIP  
Frit Seal DIP  
*H4H †H4Q  
H1B  
A
1
2
3
4
5
6
7
14 VDD  
Ceramic Flatpack  
*CD4071, CD4072  
H3W  
B
13  
12  
11  
G
H
I
†CD4075 Only  
D
E
F
K = D + E + F  
VSS  
10 L = G + H + I  
9
8
J = A + B + C  
C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3323  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-444  

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